PIC18F2331_07 Datasheet, PDF (241/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
19.4 EUSART Synchronous Master
Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit
SYNC (TXSTA<4>). In addition, enable bit SPEN
(RCSTA<7>) is set in order to configure the RC6/TX/
CK/SS and RC7/RX/DT/SDO I/O pins to CK (clock)
and DT (data) lines, respectively.
The Master mode indicates that the processor trans-
mits the master clock on the CK line. Clock polarity is
selected with the SCKP bit (BAUDCTL<4>). Setting
SCKP sets the Idle state on CK as high, while clearing
the bit, sets the Idle state low. This option is provided to
support Microwire devices with this module.
19.4.1 EUSART SYNCHRONOUS MASTER
TRANSMISSION
The EUSART transmitter block diagram is shown in
Figure 19-2. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available).
Once the TXREG register transfers the data to the TSR
register (occurs in one TCYCLE), the TXREG is empty
and interrupt bit TXIF (PIR1<4>) is set. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless
of the state of enable bit, TXIE, and cannot be cleared
in software. It will reset only when new data is loaded
into the TXREG register.
While flag bit, TXIF, indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the sta-
tus of the TSR register. TRMT is a read-only bit which is
set when the TSR is empty. No interrupt logic is tied to
this bit, so the user must poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory, so it is not available to the user.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit, TXIE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting bit, TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE bits
in the INTCON register (INTCON<7:6>) are set.
FIGURE 19-10: SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT/
SDO Pin
RC6/TX/CK/
SS Pin
(SCKP = 0)
RC6/TX/CK/
SS pin
(SCKP = 1)
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
bit 0
bit 1
bit 2
Word 1
Write Word 1
Write Word 2
TRMT bit
TXEN bit ^{‘1’}
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 7
bit 0
bit 1
bit 7
Word 2
‘1’
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 239