PIC18F2331_07 Datasheet, PDF (261/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
20.9 A/D Conversions
Figure 20-3 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins. The internal
A/D RC oscillator must be selected to perform a
conversion in Sleep.
Figure 20-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT3:ACQT0
bits are set to ‘010’ and a 4 TAD acquisition time is
selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The resulting buffer loca-
tion will contain the partially completed A/D conversion
sample. This will not set the ADIF flag, therefore, the
user must read the buffer location before a conversion
sequence overwrites it.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 20-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
GO/DONE bit is
set and holding
cap is
disconnected
from analog
input
TAD1 TAD2 TAD3
b9 b8 b7
Conversion Starts
TAD4
b6
TAD5
b5
TAD6
b4
TAD7
b3
TAD8
b2
TAD9 TAD10 TAD11
b1 b0
GO/DONE bit cleared on the rising edge of Q1 after the first Q3
following TAD11 and result buffer is loaded.⁽¹⁾
Note 1: Conversion time is a minimum of 11 TAD + 2 TCY and a maximum of 11 TAD + 6 TCY.
FIGURE 20-4:
A/D CONVERSION TAD CYCLES (ACQT<3:0> = 0010, TACQ = 4 TAD)
TACQT Cycles
TAD Cycles
1
2
3
4 TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
Automatic
Acquisition
Time
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts
(Holding capacitor is disconnected)
A/D Triggered
GO/DONE bit cleared on the rising edge of Q1 after the first Q3
following TAD11 and result buffer is loaded.⁽¹⁾
Note 1: In Continuous modes, next conversion starts at the end of TAD12.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 259