PIC18F2331_07 Datasheet, PDF (135/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
REGISTER 10-1: TRISE REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
U-0
R/W-1
R/W-1
R/W-1
—
TRISE2
TRISE1
TRISE0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
TRISE2: RE2 Direction Control bit
1 = Input
0 = Output
TRISE1: RE1 Direction Control bit
1 = Input
0 = Output
TRISE0: RE0 Direction Control bit
1 = Input
0 = Output
TABLE 10-9: PORTE FUNCTIONS
Name
Bit # Buffer Type
RE0/AN6
bit 0
ST
RE1/AN7
bit 1
ST
RE2/AN8
bit 2
ST
MCLR/VPP/RE3 bit 3
ST
Legend: ST = Schmitt Trigger input
Function
Input/output port pin or analog input.
Input/output port pin or analog input.
Input/output port pin or analog input.
Input only port pin or programming voltage input (if MCLR is disabled);
Master Clear input or programming voltage input (if MCLR is enabled).
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
PORTE
LATE
TRISE
ANSEL0
ANSEL1
Legend:
Note 1:
2:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
—
—
—
—
RE3⁽¹⁾
RE2
RE1
RE0 ---- q000
—
—
—
—
— LATE Data Output Register
---- -xxx
—
ANS7⁽²⁾
—
—
ANS6⁽²⁾
—
—
ANS5⁽²⁾
—
—
ANS4
—
—
ANS3
—
PORTE Data Direction Register
ANS2
—
ANS1
—
ANS0
ANS8⁽²⁾
---- -111
1111 1111
---- ---1
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used by PORTE.
Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0).
ANS5 through ANS8 are available only on PIC18F4331/4431 devices.
Value on
all other
Resets
---- q000
---- -uuu
---- -111
1111 1111
---- ---1
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 133