PIC18F2331_07 Datasheet, PDF (177/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
16.2.6 VELOCITY MEASUREMENT
The velocity pulse generator, in conjunction with the
IC1 and the synchronous TMR5 (in synchronous
operation), provides a method for high accuracy speed
measurements at both low and high mechanical motor
speeds. The Velocity mode is enabled when the VELM
bit is cleared (= 0) and QEI is set to one of its operating
modes (see Table 16-6).
To optimize register space, the Input Capture
Channel 1 (IC1) is used to capture TMR5 counter
values. Input Capture Buffer register, CAP1BUF, is
redefined in Velocity Measurement mode, VELM = 0,
as the Velocity Register Buffer (VELRH, VELRL).
TABLE 16-6: VELOCITY PULSES
QEIM<2:0>
Velocity Event Mode
001 x2 Velocity Event mode. The velocity
010 pulse is generated on every QEA edge.
101 x4 Velocity Event mode. The velocity
110 pulse is generated on every QEA and
QEB active edge.
16.2.6.1 Velocity Event Timing
The event pulses are reduced by a fixed ratio by the
velocity pulse divider. The divider is useful for
high-speed measurements where the velocity events
happen frequently. By producing a single output pulse
for a given number of input event pulses, the counter
can track larger pulse counts (i.e., distance travelled)
for a given time interval. Time is measured by utilizing
the TMR5 time base.
Each velocity pulse serves as a capture pulse. With the
TMR5 in Synchronous Timer mode, the value of TMR5
is captured on every output pulse of the postscaler. The
counter is subsequently reset to ‘0’. TMR5 is reset
upon a capture event.
Figure 16-13 shows the velocity measurement timing
diagram.
FIGURE 16-12: VELOCITY MEASUREMENT BLOCK DIAGRAM
QEI
Control
Logic
Reset ^{TMR5 Reset}
Logic
TMR5 ^Clock
TCY
16
Velocity Mode
CAP3/QEB
CAP2/QEA
CAP1/INDX
Velocity Event
QEB
QEA
INDX
Direction
Clock
Velocity Capture
Postscaler
IC1
(VELR Register)
Position
Counter
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 175