PIC18F2331_07 Datasheet, PDF (229/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
19.2 EUSART Baud Rate Generator
(BRG)
The BRG is a dedicated 8-bit or 16-bit generator, that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode. Setting the BRG16 bit (BAUDCTL<3>)
selects 16-bit mode.
The SPBRGH:SPBRG register pair controls the period
of a free-running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 also control the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 19-1 shows the formula for computation of the
baud rate for different EUSART modes, which only
apply in Master mode (internally generated clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 19-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 19-1. Typical baud
rates and error values for the various Asynchronous
modes are shown in Table 19-2. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG, to reduce the baud rate error or
achieve a slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
19.2.1 POWER-MANAGED MODE
OPERATION
The system clock is used to generate the desired baud
rate. However, when a power-managed mode is
entered, the clock source may be operating at a
different frequency than in PRI_RUN mode. In Sleep
mode, no clocks are present and in PRI_IDLE, the
primary clock source continues to provide clocks to the
Baud Rate Generator. However, in other power-
managed modes, the clock frequency will probably
change. This may require the value in SPBRG to be
adjusted.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit
and make sure that the receive operation is Idle before
changing the system clock.
19.2.2 SAMPLING
The data on the RC7/RX/DT/SDO pin is sampled three
times by a majority detect circuit to determine if a high
or a low level is present at the RX pin.
TABLE 19-1: BAUD RATE FORMULAS
Configuration Bits
SYNC
BRG16
BRGH
BRG/EUSART Mode
0
0
0
0
1
1
Legend:
0
0
8-Bit/Asynchronous
0
1
8-Bit/Asynchronous
1
0
16-Bit/Asynchronous
1
1
16-Bit/Asynchronous
0
x
8-Bit/Synchronous
1
x
16-Bit/Synchronous
x = Don’t care, n = value of SPBRGH:SPBRG register pair
Baud Rate Formula
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 227