PIC18F2331_07 Datasheet, PDF (47/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
3.6.1 EXAMPLE – EUSART
An adjustment may be indicated when the EUSART
begins to generate framing errors, or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the system clock frequency is too high –
try decrementing the value in the OSCTUNE register to
reduce the system clock frequency. Errors in data
may suggest that the system clock speed is too low –
increment OSCTUNE.
3.6.2 EXAMPLE – TIMERS
This technique compares system clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast – decrement OSCTUNE.
3.6.3 EXAMPLE – CCP IN CAPTURE MODE
A CCP module can use free-running Timer1, clocked
by the internal oscillator block and an external event
with a known period (i.e., AC power frequency). The
time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the calculated
time, the internal oscillator block is running too fast –
decrement OSCTUNE. If the measured time is much
less than the calculated time, the internal oscillator block
is running too slow – increment OSCTUNE.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 45