PIC18F2331_07 Datasheet, PDF (254/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
The A/D channels are grouped into four sets of 2 or 3
channels. For the PIC18F2331/2431 devices, AN0 and
AN4 are in Group A, AN1 is in Group B, AN2 is in Group
C and AN3 is in Group D. For the PIC18F4331/4431
devices, AN0, AN4 and AN8 are in Group A, AN1 and
AN5 are in Group B, AN2 and AN6 are in Group C and
AN3 and AN7 are in Group D. The selected channel in
each group is selected by configuring the A/D Channel
Select Register, ADCHS.
The analog voltage reference is software selectable to
either the device’s positive and negative analog supply
voltage (AVDD and AVSS), or the voltage level on the
RA3/AN3/VREF+/CAP2/QEA and RA2/AN2/VREF-/
CAP1/INDX, or some combination of supply and
external sources. Register ADCON1 controls the
voltage reference settings.
FIGURE 20-1:
A/D BLOCK DIAGRAM
VREF+
VREF-
AVDD AVSS
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can
individually be configured as an analog input or digital
I/O using the ANSEL0 and ANSEL1 registers. The
ADRESH and ADRESL registers contain the value in
the result buffer pointed to by ADPNT<1:0>
(ADCON1<1:0>). The result buffer is a 4-deep circular
buffer that has a Buffer Empty status bit, BFEMT
(ADCON1<3>), and a Buffer Overflow status bit,
BFOVFL (ADCON1<2>).
VCFG<1:0>
AN0
AN4
AN8⁽¹⁾
AN2/VREF-
AN6⁽¹⁾
Analog
MUX
VREFL
VREFH
ADC
ADRESH, ADRESL
10
MUX
ADPNT<1:0>
AN1
AN5⁽¹⁾
AN3/VREF+
AN7⁽¹⁾
ACMOD<1:0>,
GxSEL<1:0>
Analog
MUX
ACMOD<1:0>,
GxSEL<1:0>
S/H-1
+
S/H
-
AVSS
ACONV
ACSCH
ACMODx
S/H-2
+
S/H
-
AVSS
Seq.
Cntrl.
1
2
3
4
4x10-Bit FIFO
00
01
10
11
Note 1: AN5 through AN8 are available only on PIC18F4331/4431 devices.
DS39616C-page 252
Preliminary
© 2007 Microchip Technology Inc.