PIC18F2331_07 Datasheet, PDF (218/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 18-1:
SSP BLOCK DIAGRAM
(SPI MODE)
Read
Internal
Data Bus
Write
SSPBUF Reg
SDI
SDO
SS
SCK
SSPSR Reg
bit 0
Shift
Clock
Peripheral OE
SS Control
Enable
Edge
Select
2
Clock Select
SSPM3:SSPM0
TMR2 Output
4
2
Edge
Select
TRISC<3>
Prescaler TCY
4, 16, 64
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>), must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, reinitialize the SSPCON
register and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, they must
have their data direction bits (in the TRISC register)
appropriately programmed. That is:
• Serial Data Out (SDO) – RC7/RX/DT/SDO or
RD1/SDO
• SDI must have TRISC<4> or TRISD<2> set
• SDO must have TRISC<7> or TRISD<1> cleared
• SCK (Master mode) must have TRISC<5> or
TRISD<3> cleared
• SCK (Slave mode) must have TRISC<5> or
TRISD<3> set
• SS must have TRISA<6> set
Note 1: When the SPI is in Slave mode with
the SS pin control enabled
(SSPCON<3:0> = 0100), the SPI module
will reset if the SS pin is set to VDD.
2: If the SPI is used in Slave mode with
CKE = 1, then the SS pin control must be
enabled.
3: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the state of the SS pin can affect the state
read back from the TRISC<6> bit. The
peripheral OE signal from the SSP module
into PORTC controls the state that is read
back from the TRISC<6> bit (see
Section 10.3 “PORTC, TRISC and LATC
Registers” for information on PORTC). If
Read-Modify-Write instructions, such as
BSF, are performed on the TRISC register
while the SS pin is high, this will cause the
TRISC<6> bit to be set, thus disabling the
SDO output.
DS39616C-page 216
Preliminary
© 2007 Microchip Technology Inc.