PIC18F2331_07 Datasheet, PDF (223/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
18.3.1.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set. This is an error
condition due to the user’s firmware.
An SSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
FIGURE 18-6:
I²C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
SDA
A7
Receiving Address
A6 A5 A4 A3 A2
R/W = 0
A1
ACK
D7
Receiving Data
D6 D5 D4 D3 D2
D1
ACK
D0
D7
D6
Receiving Data
D5 D4 D3 D2
D1
ACK
D0
SCL S ^{1 2 3 4} 5 ^{6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9}
P
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
Cleared in software
SSPBUF register is read
Bit SSPOV is set because the SSPBUF register is still full
ACK is not sent
Bus master
terminates
transfer
18.3.1.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin SCK/SCL is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then,
pin SCK/SCL should be enabled by setting bit CKP
(SSPCON<4>). The master must monitor the SCL pin
prior to asserting another clock pulse. The slave
devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling
edge of the SCL input. This ensures that the SDA signal
is valid during the SCL high time (Figure 18-7).
An SSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF, must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. Flag bit, SSPIF, is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then the
data transfer is complete. When the ACK is latched by
the slave, the slave logic is reset (resets SSPSTAT
register) and the slave then monitors for another
occurrence of the Start bit. If the SDA line was low (ACK),
the transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then pin
SCK/SCL should be enabled by setting bit CKP.
FIGURE 18-7:
I²C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
Receiving Address
R/W = 1
A7 A6 A5 A4 A3 A2 A1
ACK
Transmitting Data ACK
D7 D6 D5 D4 D3 D2 D1 D0
SCL _S
1 23456789
1 2 34 56 789
Data in
SCL held low
P
sampled
while CPU
responds to SSPIF
SSPIF (PIR1<3>)
Cleared in software
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
SSPBUF is written in software
From SSP Interrupt
Service Routine
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 221