PIC18F2331_07 Datasheet, PDF (72/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
EEADR
EEPROM Address Register
0000 0000 52, 87
EEDATA
EEPROM Data Register
0000 0000 52, 90
EECON2
EEPROM Control Register 2 (not a physical register)
0000 0000 52, 78, 87
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 52, 79, 88
IPR3
—
—
—
PTIP
IC3DRIP IC2QEIP
IC1IP
TMR5IP ---1 1111 52, 106
PIR3
—
—
—
PTIF
IC3DRIF IC2QEIF
IC1IF
TMR5IF ---0 0000 52, 100
PIE3
—
—
—
PTIE
IC3DRIE IC2QEIE
IC1IE
TMR5IE ---0 0000 52, 103
IPR2
OSCFIP
—
—
EEIP
—
LVDIP
—
CCP2IP 1--1 -1-1 53, 105
PIR2
OSCFIF
—
—
EEIF
—
LVDIF
—
CCP2IF 0--0 -0-0 53, 99
PIE2
OSCFIE
—
—
EEIE
—
LVDIE
—
CCP2IE 0--0 -0-0 53, 102
IPR1
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP TMR2IP TMR1IP -111 1111 53, 104
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF -000 0000 53, 98
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE -000 0000 53, 101
OSCTUNE
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0 --00 0000 27, 53
ADCON3
ADRS1
ADRS0
—
SSRC4
SSRC3
SSRC2
SSRC1
SSRC0 00-0 0000
52
ADCHS
TRISE⁽⁵⁾
TRISD⁽⁵⁾
GDSEL1 GDSEL0 GBSEL1
—
—
—
PORTD Data Direction Register
GBSEL0
—
GCSEL1 GCSEL0 GASEL1 GASEL0
—
PORTE Data Direction Register⁽⁵⁾
0000 0000
---- -111
1111 1111
52
53, 133
53, 130
TRISC
PORTC Data Direction Register
1111 1111 53, 125
TRISB
TRISA
PORTB Data Direction Register
TRISA7⁽²⁾ TRISA6⁽¹⁾ PORTA Data Direction Register
1111 1111
1111 1111
53, 119
53, 113
PR5H
Timer5 Period Register High Byte
1111 1111
52
PR5L
Timer5 Period Register Low Byte
LATE⁽⁵⁾
—
—
—
—
—
LATE Data Output Register
LATD⁽⁵⁾
LATD Data Output Register
1111 1111
---- -xxx
xxxx xxxx
52
53, 133
53, 130
LATC
LATC Data Output Register
xxxx xxxx 53, 125
LATB
LATA
LATB Data Output Register
LATA7⁽²⁾ LATA6⁽¹⁾ LATA Data Output Register
xxxx xxxx
xxxx xxxx
53, 119
53, 113
TMR5H
Timer5 Register High Byte
xxxx xxxx
148
TMR5L
PORTE
PORTD⁽⁵⁾
Timer5 Register Low Byte
—
—
RD7
RD6
—
RD5
—
RD4
RE3⁽⁶⁾
RD3
RE2⁽⁵⁾
RD2
RE1⁽⁵⁾
RD1
RE0⁽⁵⁾
RD0
xxxx xxxx
---- xxxx
xxxx xxxx
148
53, 133
53, 130
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx 53, 125
PORTB
PORTA
RB7
RA7⁽²⁾
RB6
RA6⁽¹⁾
RB5
RA5
RB4
RA4
RB3
RA3
RB2
RA2
RB1
RA1
RB0
xxxx xxxx 53, 119
RA0
xx0x 0000 53, 113
PTCON0
PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000 54, 186
PTCON1
PTEN
PTDIR
—
—
—
—
—
—
00-- ---- 54, 186
PTMRL
PWM Time Base Register (lower 8 bits)
0000 0000
184
PTMRH
UNUSED
PWM Time Base Register (upper 4 bits)
---- 0000
184
PTPERL
PWM Time Base Period Register (lower 8 bits)
1111 1111
184
PTPERH
UNUSED
PWM Time Base Period Register (upper 4 bits)
---- 1111
184
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital inputs and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as
analog inputs and read ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 reads ‘0’. This bit is read-only.
DS39616C-page 70
Preliminary
© 2007 Microchip Technology Inc.