PIC18F2331_07 Datasheet, PDF (123/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 10-14: BLOCK DIAGRAM OF RC1
PORT/CCP2 Select
CCP2 Data Out
0
RD LATC
1
Data Bus
WR LATC
or PORTC
D
Q
CK Q
Data Latch
WR TRISC
D
Q
CK Q
TRIS Latch
VDD
To RC0 Pin
P
RC1 Pin
N
VSS
RD TRISC
RD PORTC
CCP2 Input
FLTA Input⁽¹⁾
Q
D
EN
Schmitt
Trigger
FLTAMX
Note 1: FLTA input is multiplexed with RC1 and RD4 using FLTAMX Configuration bit in CONFIG3H register.
FIGURE 10-15: BLOCK DIAGRAM OF RC2
PORT/CCP1 Select
CCP1 Data Out
0
RD LATC
1
Data Bus
WR LATC
or PORTC
D
Q
CK Q
Data Latch
D
Q
WR TRISC
CK Q
TRIS Latch
VDD
P
RC2 Pin
N
VSS
RD TRISC
RD PORTC
CCP1 Input/FLTB Input
Q
D
EN
Schmitt
Trigger
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 121