PIC18F2331_07 Datasheet, PDF (190/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
REGISTER 17-4: PWMCON1: PWM CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR
—
bit 7
R/W-0
UDIS
R/W-0
OSYNC
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
bit 3
bit 2
bit 1
bit 0
SEVOPS3:SEVOPS0: PWM Special Event Trigger Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
.
.
.
1111 = 1:16 Postscale
SEVTDIR: Special Event Trigger Time Base Direction bit
1 = A Special Event Trigger will occur when the PWM time base is counting downwards
0 = A Special Event Trigger will occur when the PWM time base is counting upwards
Unimplemented: Read as ‘0’
UDIS: PWM Update Disable bit
1 = Updates from Duty Cycle and Period Buffer registers are disabled
0 = Updates from Duty Cycle and Period Buffer registers are enabled
OSYNC: PWM Output Override Synchronization bit
1 = Output overrides via the OVDCON register are synchronized to the PWM time base
0 = Output overrides via the OVDCON register are asynchronous
17.3.1 FREE-RUNNING MODE
In the Free-Running mode, the PWM Time Base regis-
ters (PTMRL and PTMRH) will begin counting upwards
until the value in the PWM Time Base Period register,
PTPER (PTPERL and PTPERH), is matched. The
PTMR registers will be reset on the following input
clock edge and the time base will continue counting
upwards as long as the PTEN bit remains set.
17.3.2 SINGLE-SHOT MODE
In the Single-Shot mode, the PWM time base will begin
counting upwards when the PTEN bit is set. When the
value in the PTMR register matches the PTPER regis-
ter, the PTMR register will be reset on the following
input clock edge and the PTEN bit will be cleared by the
hardware to halt the time base.
17.3.3 CONTINUOUS UP/DOWN COUNT
MODES
In Continuous Up/Down Count modes, the PWM time
base counts upwards until the value in the PTPER
register matches with the PTMR register. On the
following input clock edge, the timer counts
downwards. The PTDIR bit in the PTCON1 register is
read-only and indicates the counting direction. The
PTDIR bit is set when the timer counts downwards.
Note:
Since the PWM compare outputs are
driven to the active state when the PWM
time base is counting downwards and
matches the duty cycle value, the PWM
outputs are held inactive during the first
half of the first period of the Continuous
Up/Down Count mode until PTMR begins
to count down from the PTPER value.
17.3.4 PWM TIME BASE PRESCALER
The input clock to PTMR (FOSC/4) has prescaler
options of 1:1, 1:4, 1:16 or 1:64. These are selected by
control bits, PTCKPS<1:0>, in the PTCON0 register.
The prescaler counter is cleared when any of the
following occurs:
• Write to the PTMR register
• Write to the PTCON (PTCON0 or PTCON1)
register
• Any device Reset
Note: The PTMR register is not cleared when
PTCONx is written.
DS39616C-page 188
Preliminary
© 2007 Microchip Technology Inc.