82378ZB Datasheet, PDF (99/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
Counter 0, System Timer: This counter functions as the system timer by controlling the state of IRQ0 and is
typically programmed for Mode 3 operation. The counter produces a square wave with a period equal to the
product of the counter period (838 ns) and the initial count value. The counter loads the initial count value one
counter period after software writes the count value to the counter I/O address. The counter initially asserts
IRQ0 and decrements the count value by two each counter period. The counter negates IRQ0 when the count
value reaches 0. It then reloads the initial count value and again decrements the initial count value by two each
counter period. The counter then asserts IRQ0 when the count value reaches 0, reloads the initial count value,
and repeats the cycle, alternately asserting and negating IRQ0.
Counter 1, Refresh Request Signal: This counter provides the refresh request signal and is typically
programmed for Mode 2 operation. The counter negates refresh request for one counter period (833 ns) during
each count cycle. The initial count value is loaded one counter period after being written to the counter I/O
address. The counter initially asserts refresh request, and negates it for 1 counter period when the count value
reaches 1. The counter then asserts refresh request and continues counting from the initial count value.
Counter 2, Speaker Tone: This counter provides the speaker tone and is typically programmed for Mode 3
operation. The counter provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided
by the initial count value. The speaker must be enabled by a write to Port 061h (see Register Description
section).
NOTE
1. In the PC-AT architecture, the three interval timers in the 82C54 perform the following functions Timer 1 is
the System timer, Timer 2 provides the refresh request, and Timer 3 is used for the speaker tone. The
interval timer in the SIO/SIO.A, are intended to be used for these functions. Other operations are not
supported and may produce unintended operations. In other than these operations, the timer may be in a
state where a counter can be read at the same time it’s count is changing and an incorrect value is latched.
The readback and latch commands are also affected.
2. Hardware re-triggerable one-shot mode (timer mode 1) for timer 2. This mode uses a rising edge on the timer
GATE input to start the timer. The timer GATE input can be toggled by writing to I/O port 61H. Because the
GATE pin is asserted relative to PCICLK, the setup and hold time requirements of the GATE pin relative to
the 82C54 OSC clock can be violated. Because GATE is edge triggered in timer mode 1, the 82C54 does not
recognize the rising edge and the timer does not begin counting. In the PC-AT architecture, timer 2 is the only
timer that has its GATE input connected to an I/O port. All the other GATE inputs are tied high. This condition
was uncovered during 82C54 diagnostic testing. No application failures have been reported due to this issue.
4.7.2. BIOS TIMER
The SIO/SIO.A provides a system BIOS Timer that decrements at each edge of its 1.04 MHz clock (derived by
dividing the 8.33 MHz SYSCLK by 8). Since the state of the counter is undefined at power-up, it must be
programmed before it can be used. Accesses to the BIOS Timer are enabled and disabled through the BIOS
Timer Base Address Register. The timer continues to count even if accesses are disabled.
A BIOS Timer Register is provided to start the timer counter by writing an initial clock value. The BIOS Timer
Register can be accessed as a single 16-bit I/O port or as a 32-bit port with the upper 16-bits being "don't care"
(reserved). It is up to the software to access the I/O Register in the most convenient way. The I/O address of the
BIOS Timer Register is software relocatable. The I/O address is determined by the value programmed into the
BIOS Timer Base Address Register.
The BIOS Timer clock has a value of 1.04 MHz using an 8.33 MHz SYSCLK input (an 8-to-1 ratio will always
exist between SYSCLK and the timer clock). This allows the counting of time intervals from 0 to approximately
65 ms. Because of the PCI clock rate, it is possible to start the counter and read the value back in less than 1
µs. The expected value of the expired interval is 0, but depending on the state of the internal clock divisor, the
BIOS Timer might indicate that 1 ms has expired. Therefore, accuracy of the counter is ± 1 µs.
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