82378ZB Datasheet, PDF (98/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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4.6. Data Buffering
The SIO/SIO.A contains data buffers to isolate the PCI Bus from the ISA Bus. The buffering is described from
two perspectives: PCI master accesses to the ISA Bus (Posted Write Buffer) and DMA/ISA master accesses to
the PCI Bus (Line Buffer). Temporarily buffering the data requires buffer management logic to ensure that the
data buffers remain coherent.
4.6.1. DMA/ISA MASTER LINE BUFFER
An 8-byte Line Buffer is used to isolate the ISA Bus's slower I/O devices from the PCI Bus. The Line Buffer is bi-
directional and is used by ISA masters and the DMA controller to assemble and disassemble data. Only memory
data written to or read from the PCI Bus by an ISA master or DMA is assembled/disassembled using this 8-byte
line buffer. I/O cycles do not use the buffer.
Bits 0 and 1 of the PCI Control Register set the buffer to operate in either single transaction mode (bit=0) or
8-byte mode (bit=1). Note that ISA masters and DMA controllers can have their buffer modes configured
separately.
In single transaction mode, the buffer will store only one transaction. For DMA/ISA master writes, this single
transaction buffer looks like a posted write buffer. As soon as the ISA cycle is complete, a PCI cycle is
scheduled. Subsequent DMA/ISA master writes are held off in wait-states until the buffer is empty. For DMA/ISA
master reads, only the data requested is read over the PCI Bus. For instance, if the DMA channel is
programmed in 16-bit mode, 16 bits of data will be read from PCI. As soon as the requested data is valid on the
PCI Bus, it is latched into the Line Buffer and the ISA cycle is then completed, as timing allows. Single
transaction mode will guarantee strong read and write ordering through the buffers.
In 8-byte mode, for write data assembly, the Line Buffer acts as two individual 4 byte buffers working in ping
pong fashion. For read data disassembly, the Line Buffer acts as one 8-byte buffer.
4.6.2. PCI MASTER POSTED WRITE BUFFER
PCI master memory write cycles destined to ISA memory are buffered in a 32-bit Posted Write Buffer. The PCI
Memory Write and Memory Write and Invalidate commands are all treated as a memory write and can be
posted, subject to the Posted Write Buffer status. The Posted Write Buffer has an address associated with it. A
PCI master memory write can be posted any time the posted write buffer is empty and write posting is enabled
(bit 2 of the PCI Control Configuration Register is set to a 1). Also, the ISA Bus must not be occupied. If the
posted write buffer contains data, the PCI master write cycle is retried. If the posted write buffer is disabled, the
SIO/SIO.A response to a PCI master memory write is dependent on the state of the ISA Bus. If the ISA Bus is
available and the posted write buffer is disabled, the cycle will immediately be forwarded to the ISA Bus (TRDY#
will not be asserted until the ISA cycle has completed). If the ISA Bus is busy and the posted write buffer is
disabled, the cycle is retried. Memory read and I/O read and I/O write cycles do not use the 32-bit Posted Write
Buffer.
4.7. SIO Timers
4.7.1. INTERVAL TIMERS
The SIO/SIO.A contains three counters that are equivalent to those found in the 82C54 programmable interval
timer. The three counters are contained in one SIO/SIO.A timer unit, referred to as Timer-1. Each counter output
provides a key system function. Counter 0 is connected to interrupt controller IRQ0 and provides a system timer
interrupt for a time-of-day, diskette time-out, or other system timing functions. Counter 1 generates a refresh
request signal and Counter 2 generates the tone for the speaker. Note that the 14.31818 MHz counters use
OSC for a clock source.
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