82378ZB Datasheet, PDF (35/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
3.1.6. PCICON—PCI CONTROL REGISTER
Address Offset:
Default Value:
Attribute:
40h
20h
Read/Write
This 8-bit register controls the Line Buffer operation, the SIO/SIO.A PCI Posted Write Buffer enabling, and the
DEVSEL# signal sampling point. The PCICON Register also controls how the SIO/SIO.A responds to INTA
cycles on the PCI Bus and if the reserved DMA page registers are aliased from 80h-8Fh to 90h-9Fh.
Bit
Description
7 Reserved: Read as 0.
6 DMAAC (DMA Reserved Page Register Aliasing Control): This bit controls whether the SIO/SIO.A
aliases I/O accesses in the 80h-8Fh to the 90h-9Fh range. When DMAAC=0, the SIO/SIO.A aliases I/O
accesses in the 80h-8Fh to the 90h-9Fh range (AD4 is not used for decoding the DMA reserved page
registers). When DMAAC=1, the SIO/SIO.A only respond to the 80h-8Fh range (AD4 is used for
decoding the DMA reserved page registers). Read and write accesses to the 90h-9Fh range will be
forwarded from the PCI Bus to the ISA Bus.
NOTE
I/O Port 92h is always a distinct register in the 90h-9Fh range and is always fully decoded, regardless
of the setting of this bit.
5 IAE (Interrupt Acknowledge Enable): When IAE=0, the SIO/SIO.A ignores INTA cycles generated
on the PCI Bus. However, when disabled, the SIO/SIO.A still responds to accesses to the 8259's
register set and allows poll mode functions. When IAE=1, the SIO/SIO.A responds to INTA cycles in the
normal fashion.
4:3 SDSP (Subtractive Decoding Sample Point): The SDSP field determines the DEVSEL# sample
point, after which an inactive DEVSEL# results in the SIO/SIO.A forwarding the unclaimed PCI cycle to
the ISA Bus (subtractive decoding). This setting should match the slowest device in the system.
Bit[4:3]
00
01
Operation
Slow sample point
Typical sample point
Bit[4:3]
10
11
Operation
Fast sample point
Reserved
2 PPBE (PCI Posted Write Buffer Enable): When PPBE=0 (default), the PCI posted write buffer is
disabled. When PPBE=1, the PCI posted write buffer is enabled.
1 ILBC (ISA Master Line Buffer Configuration): When ILBC=0 (default), the Line Buffer is in single
transaction mode. When ILBC=1, the Line Buffer is in 8-byte mode. This bit applies only to ISA Master
transfers.
0 DLBC (DMA Line Buffer Configuration): When DLBC=0 (default), the Line Buffer is in single
transaction mode. When DLBC=1, the Line Buffer is in 8-byte mode. This bit applies only to DMA
transfers.
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