82378ZB Datasheet, PDF (61/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
3.2.8. DMA BASE AND CURRENT ADDRESS REGISTERS (8237 COMPATIBLE SEGMENT)
Address Offset:
Default Value:
Attribute:
DMA Channel 0000h; DMA Channel 40C0h
DMA Channel 1002h; DMA Channel 50C4h
DMA Channel 2004h; DMA Channel 60C8h
DMA Channel 3006h; DMA Channel 70CCh
All bits undefined
Read/Write
Each channel has a 16-bit Current Address Register. For the 82378ZB, this register contains the value of the 16
least significant bits of the full 32-bit address used during DMA transfers. For the 82379AB, this register contains
the value of the 16 least significant bits of the full 27-bit address used during DMA transfers.
The address is automatically incremented or decremented after each transfer and the intermediate values of the
address are stored in the Current Address Register during the transfer. This register is written to or read from by
the PCI Bus or ISA Bus master in successive 8-bit bytes. The programmer must issue the "Clear Byte Pointer
Flip-Flop" command to reset the internal byte pointer and correctly align the write prior to programming the
Current Address Register. Autoinitialize takes place only after a TC or EOP.
For the 82378ZB in S/G mode, these registers store the lowest 16 bits of the current memory address. During an
S/G transfer, the DMA will load a reserve buffer into the base memory address register.
Bit
Description
15:0 Base and Current Address [15:0]. These bits represent address bits[15:0] used when foming the
address for DMA transfers. Upon PCIRST# or Master Clear, the value of these bits is 0000h.
3.2.9. DMA BASE AND CURRENT BYTE/WORD COUNT REGISTERS (8237 COMPATIBLE SEGMENT)
Address Offset:
Default Value:
Attribute:
DMA Channel 0001h DMA Channel 40C2h
DMA Channel 1003h DMA Channel 50C6h
DMA Channel 2005h DMA Channel 60CAh
DMA Channel 3007h DMA Channel 70CEh
All bits undefined
Read/Write
This register determines the number of transfers to be performed. The actual number of transfers is one more
than the number programmed in the Current Byte/Word Count Register. The Byte/Word count is decremented
after each transfer. When the value in the register goes from zero to 0FFFFh, a TC is generated. Following the
end of a DMA service the register may also be re-initialized by an autoinitialization back to its original value.
Autoinitialize can only occur when a TC occurs. If it is not autoinitialized, this register has a count of FFFFh after
TC.
For transfers to/from an 8-bit I/O, the Byte/Word count indicates the number of bytes to be transferred. For
transfers to/from a 16-bit I/O, with shifted address, the Byte/Word count indicates the number of 16-bit words to
be transferred. When the Extended Mode Register is programmed for transfers to/from a 16-bit I/O, the
Byte/Word Count indicates the number of bytes to be transferred. The number of bytes does not need to be a
multiple of two or four in this case.
61