82378ZB Datasheet, PDF (23/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
Signal Name Type
Description
ECSEN#
O
ENCODED CHIP SELECT ENABLE: ECSEN# is used to determine which of the
two external 74F138 decoders is to be selected. ECSEN# is driven low to select
decoder 1 and driven high to select decoder 2. This signal is driven valid/invalid
from the SA[16:0] and LA[23:17] address lines (except for the generation of
RTCALE#, in which case, ECSEN# is driven active based on IOW# falling, and
remains active for two SYSCLKs). During a non-valid address or during an access
not targeted for the Utility Bus, this signal is driven high. Upon PCIRST#, this signal
is driven high.
ALT_RST# O
ALTERNATE RESET: ALT_RST# is used to reset the CPU under program control.
This signal is AND'ed together externally with the reset signal (KBDRST#) from the
keyboard controller to provide a software means of resetting the CPU. This provides
a faster means of reset than is provided by the keyboard controller. Writing a 1 to bit
0 in the Port 92 Register causes this signal to pulse low for approximately 4
SYSCLKs. Before another ALT_RST# pulse can be generated, bit 0 must be set to
0. Upon PCIRST#, this signal is driven inactive high (bit 0 in the Port 92 Register is
set to 0).
ALT_A20
O
ALTERNATE A20: ALT_A20 is used to force A20M# to the CPU low for support of
real mode compatible software. This signal is externally OR'ed with the A20GATE
signal from the keyboard controller and CPURST to control the A20M# input of the
CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low
drives A20M# to the CPU low, if A20GATE from the keyboard controller is also low.
Writing a 1 to bit 1 of the Port 92 Register force ALT_A20 high. ALT_A20 high drives
A20M# to the CPU high, regardless of the state of A20GATE from the keyboard
controller. Upon reset, this signal is driven low.
DSKCHG
I
DISK CHANGE: DSKCHG is tied directly to the DSKCHG signal of the floppy
controller. This signal is inverted and driven on SD7 during I/O read cycles to floppy
address locations 3F7h (primary) or 377h (secondary) as shown in the table below.
Note that the primary and secondary locations are programmed in the Utility Bus
Address Decode Enable/Disable Register "A".
FLOPPYCS# IDECSx#
Decode
Decode
State of SD7 (output) State of UBUSOE#
Enabled
Enabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Tri-stated
Driven via DSKCHG
Tri-stated
Tri-stated
Enabled
Disabled
Enabled (note)
Disabled
NOTE:
For this mode to be supported, extra logic is required to disable the U-Bus transceiver for
accesses to 3F7/377. This is necessary because of potential contention between the Utility
Bus buffer and a floppy on the ISA Bus driving the system bus at the same time during shared
I/O accesses.
This signal is also used to determine if the floppy controller is present on the Utility
Bus. It is sampled on the trailing edge of PCIRST#, and if high, the floppy is present.
For systems that do not support a floppy via the SIO/SIO.A, this pin should be
strapped low. If sampled low, the SD7 function, UBUSOE#, and ECSADDR[2:0]
signals will not be enabled for DMA or programmed I/O accesses to the floppy disk
controller. This condition overrides the floppy decode enable bits in the Utility Bus
Chip Select A.
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