82378ZB Datasheet, PDF (76/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
3.4.8. OCW3—OPERATIONAL CONTROL WORD 3 REGISTER
Address Offset:
Default Value:
Attribute:
INT CNTRL-1—020h; INT CNTRL-2—0A0h
Bit[6,0]=0, Bit[7,4:2]=undefined, Bit[5,1]=1
Read/Write
OCW3 serves three important functions: Enable Special Mask Mode, Poll Mode control, and IRR/ISR register
read control.
Bit
Description
7 Reserved: Must be 0.
6 SMM (Special Mask Mode): If ESMM=1 and SMM=1 the interrupt controller enters Special Mask
Mode. If ESMM=1 and SMM=0, the interrupt controller is in normal mask mode. When ESMM=0, SMM
has no effect.
5 ESMM (Enable Special Mask Mode): 1=Enable SMM bit; 0=Disable SMM bit.
4:3 OCW3 Select: Must be programmed to 01 selecting OCW3.
2 Poll Mode Command: 0=Disable Poll command. When bit 2=1, the next I/O read to the interrupt
controller is treated as an interrupt acknowledge cycle representing the highest priority level requesting
service.
1:0 Register Read Command: Bits[1:0] provide control for reading the In-Service Register (ISR) and the
Interrupt Request Register (IRR). When bit 1=0, bit 0 will not affect the register read selection. When bit
1=1, bit 0 selects the register status returned following an OCW3 read. If bit 0=0, the IRR will be read. If
bit 0=1, the ISR will be read. Following ICW initialization, the default OCW3 port address read will be
"read IRR". To retain the current selection (read ISR or read IRR), always write a 0 to bit 1 when
programming this register. The selected register can be read repeatedly without reprogramming OCW3.
To select a new status register, OCW3 must be reprogrammed prior to attempting the read.
Bit[1:0]
00
01
Function
No Action
No Action
Bit[1:0]
10
11
Function
Read IRQ Register
Read IS Register
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