82378ZB Datasheet, PDF (37/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
3.1.8. PAPC—PCI ARBITER PRIORITY CONTROL REGISTER
Address Offset:
Default Value:
Attribute:
42h
04h
Read/Write
This register controls the PCI arbiter priority scheme. The arbiter supports six masters arranged through four
switching banks. This permits the six masters to be arranged in a purely rotating priority scheme, one of 24 fixed
priority schemes, or a hybrid combination of the fixed and rotating priority schemes. If both fixed and rotate
modes are enabled for the same bank, the bank will be in rotate mode. For example, if both bits 0 and 4 are set
to a 1, bank 0 will be in rotate mode. For each bit, 1=Enable and 0=Disable.
Bit
Description
Bit
Description
7
Bank 3 Rotate Control
3
Bank 2 Fixed Priority Mode Select B
6
Bank 2 Rotate Control
2
Bank 2 Fixed Priority Mode Select A
5
Bank 1 Rotate Control
1
Bank 1 Fixed Priority Mode Select
4
Bank 0 Rotate Control
0
Bank 0 Fixed Priority Mode Select
Fixed Rotate
Control Control
Bank 0 Bank 0
SIOREQ#
REQ0#
0 _{Bank 0}
1
REQ1#
REQ2#
CPUREQ#
REQ3#
0
Bank 3
1
Fixed Rotate
Control Control
Bank 3 Bank 3
0
1 ^{Bank 1}
00
01 Bank 2
10
Fixed
Control
Bank 2
(a,b)
Rotate
Control
Bank 2
Fixed Rotate
Control Control
Bank 1 Bank 1
057101
NOTE: SIOREQ#/SIOGNT# are SIO/SIO.A internal signals.
Figure 1. Arbiter Configuration Diagram
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