82378ZB Datasheet, PDF (90/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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4.3. PCI Arbitration Controller
The SIO/SIO.A contains a PCI Bus arbiter that supports six PCI masters; the Host Bridge, SIO/SIO.A, and two
other masters. The SIO/SIO.A REQ#/GNT# lines are internal. The integrated arbiter can be disabled by
asserting CPUREQ# during PCIRST#. When disabled, the SIO/SIO.A REQ#, GNT#, and RESUME# signals
become visible for an external arbiter. The internal arbiter is enabled upon power-up.
The internal arbiter contains several features that contribute to system efficiency:
• Use of a RESUME# signal to re-enable a backed-off initiator in order to minimize PCI Bus thrashing when the
SIO/SIO.A generates a retry.
• A programmable timer to re-enable retried initiators after a programmable number of PCICLKs.
• The CPU (host bridge) can be optionally parked on the PCI Bus.
• A programmable PCI Bus lock or PCI resource lock function.
The PCI arbiter is also responsible for control of the Guaranteed Access Time (GAT) mode signals.
4.3.1. ARBITRATION SIGNAL PROTOCOL
The internal arbiter follows the PCI arbitration method as outlined in the Peripheral Component Interconnect
(PCI) Specification. The PCI arbitration priority scheme is programmable through the PCI Arbiter Priority Control
and Arbiter Priority Control Extension Register. See the Register Description section for further discussions on
arbitration priority.
NOTE
1. The SIO /SIO.A as a master does not generate fast back-to-back accesses.
2. As a target, the SIO/SIO.A does support back-to-back transactions. For back-to-back cycles, the
SIO/SIO.A treats positively decoded accesses and subtractively decoded accesses as different
targets. Therefore, masters can only run fast back-to-back cycles to positively decoded addresses
or to subtractively decoded addresses.
3. Before an ISA master or the DMA can be granted the PCI Bus, it is necessary that all PCI system
posted write buffers be flushed (including the SIO/SIO.A Posted Write Buffer). Also, since the ISA
originated cycle could access memory on the host bridge, it's possible that the ISA master or the
DMA could be held in wait states (via IOCHRDY) waiting for the host bridge arbitration for longer
than the 2.5 µs ISA specification. The SIO/SIO.A has an optional mode called the Guaranteed
Access Time Mode (GAT) that ensures that this timing specification is not violated.
4. An external arbiter in GAT mode will require special lo gic in the arbiter.
RETRY THRASHING RESOLVE
When a PCI initiator's access is retried, the initiator releases the PCI Bus for a minimum of two PCI clocks and
will then normally request the PCI Bus again. To avoid thrashing the bus with retry after retry, the PCI arbiter
provides REQ# masking. The REQ# masking mechanism differentiates between SIO/SIO.A target retries and all
other retries.
For initiators which were retried by the SIO/SIO.A as a target, the masked REQ# is flagged to be cleared upon
RESUME# active. All other retries trigger the Master Retry Timer, if enabled. When the timer expires, the mask
is cleared.
The conditions under which the SIO/SIO.A forces a retry to a PCI master and will mask the REQ# are:
1. Any required buffer management
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