82378ZB Datasheet, PDF (17/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
2.4. Power Management Signals
Signal Name Type
Description
SMI#
O
SYSTEM MANAGEMENT INTERRUPT: SMI# is asserted by the 82379AB in
response to one of many enableable hardware or software events. This signal is
driven low during a hard reset (PCIRST# asserted) and driven high when PCIRST#
is negated.
STPCLK#
O
STOP CLOCK: STPCLK# is asserted by the 82379AB in response to one of many
enableable hardware or software events. STPCLK# connects directly to the CPU.
This signal is driven low during a hard reset (PCIRST# asserted) and driven high
when PCIRST# is negated.
EXTSMI#
I
EXTERNAL SYSTEM MANAGEMENT INTERRUPT: EXTSMI# is a falling edge
triggered input to the 82379AB indicating that an external device is requesting the
system to enter SMM mode. This pin includes a weak internal pull-up resistor.
INIT
I
INIT: INIT is an input to the SIO/SIO.A indicating that the CPU is actually being soft
reset. It is connected to the INIT pin of the CPU. This pin includes a weak internal
pull-up resistor.
2.5. ISA Interface Signals
Signal Name Type
Description
AEN
O
ADDRESS ENABLE: AEN is asserted during DMA cycles to prevent I/O slaves
from misinterpreting DMA cycles as valid I/O cycles. This signal is also driven high
during refresh cycles. AEN is driven low upon reset.
BALE
O
BUS ADDRESS LATCH ENABLE: BALE is an active high signal asserted by the
SIO/SIO.A to indicate that the address (SA[19:0], LA[23:17]), AEN and SBHE#
signal lines are valid. The LA[23:17] address lines are latched on the trailing edge of
BALE. BALE remains asserted throughout DMA and ISA master cycles. BALE is
driven low upon reset.
SYSCLK
O
SYSTEM CLOCK: SYSCLK is an output of the SIO/SIO.A component. The
frequencies supported are 6 to 8.33 MHz.
IOCHRDY
I/O
I/O CHANNEL READY: Resources on the ISA Bus assert IOCHRDY to indicate
that additional time (wait states) is required to complete the cycle. IOCHRDY is tri-
stated upon reset.
IOCS16#
I
16-BIT I/O CHIP SELECT: This signal is driven by I/O devices on the ISA Bus to
indicate that they support 16-bit I/O bus cycles.
IOCHK#
I
I/O CHANNEL CHECK: IOCHK# can be driven by any resource on the ISA Bus.
When asserted, it indicates that a parity or an un-correctable error has occurred for
a device or memory on the ISA Bus. A NMI will be generated to the CPU if the NMI
generation is enabled.
IOR#
I/O
I/O READ: IOR# is the command to an ISA I/O slave device that the slave may
drive data on to the ISA data bus (SD[15:0]). IOR# is driven high upon reset.
IOW#
I/O
I/O WRITE: IOW# is the command to an ISA I/O slave device that the slave may
latch data from the ISA data bus (SD[15:0]). IOW# is driven high upon reset.
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