82378ZB Datasheet, PDF (22/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
2.9. APIC Bus Signals (82379AB Only)
Pin Name
Type
Description
APICCLK
in
APIC BUS CLOCK: APICCLK provides the timing reference for the APIC Bus.
Changes on APICD[1:0]# are synchronous to the rising edge of APICCLK.
APICD[1:0]
od
APIC DATA: APICD1 and APICD0 are the APIC data bus signals. Interrupt
messages are sent/received over this bus. APICD1 has a weak pull-down resistor.
These signals require external pull-ups (330 Ω recommended) to the 3.3V rail.
These signals are tri-stated during a hard reset.
2.10. Utility Bus Signals
Signal Name Type
Description
UBUSTR
O
UTILITY DATA BUS TRANSMIT/RECEIVE: UBUSTR is tied directly to the
direction control of a 74F245 that buffers the utility data bus, UD[7:0]. UBUSTR is
asserted for all I/O read cycles (regardless if a utility bus device has been decoded).
UBUSTR is asserted for memory cycles only if BIOS space has been decoded. For
PCI and ISA master-initiated read cycles, UBUSTR is asserted from the falling edge
of either IOR# or MEMR#, depending on the cycle type (driven from MEMR# only if
BIOS space has been decoded). When the rising edge of IOR# or MEMR# occurs,
the SIO/SIO.A negates UBUSTR. For DMA read cycles from the Utility Bus,
UBUSTR is asserted when DACKx# is asserted and negated when DACKx# is
negated. At all other times, UBUSTR is negated. Upon PCIRST#, this signal is
driven low.
UBUSOE# O
UTILITY DATA BUS OUTPUT ENABLE: UBUSOE# is tied directly to the output
enable of a 74F245 that buffers the utility data bus, UD[7:0], from the system data
bus, SD[7:0]. UBUSOE# is asserted anytime a SIO/SIO.A supported Utility Bus
device is decoded, and the devices decode is enabled in the Utility Bus Chip Select
Enable Registers. UBUSOE# is asserted from the falling edge of the ISA
commands (IOR#, IOW#, MEMR#, or MEMW#) for PCI and ISA master-initiated
cycles. UBUSOE# is negated from the rising edge of the ISA command signals for
SIO/SIO.A-initiated cycles and the SA[16:0] and LA[23:17] address for ISA master-
initiated cycles. For DMA cycles, UBUSOE# is asserted when DACK2# is asserted
and negated when DACK2# negated. UBUSOE# is not driven active under the
following conditions:
NOTES:
1. During an I/O access to the floppy controller, if DSKCHG is sampled low at reset.
2. If the Digital Output Register is programmed to ignore DACK2#.
3. During an I/O read access to floppy location 3F7h (primary) or 377h (secondary), if theIDE
decode space is disabled (i.e., IDE is not resident on the Utility Bus).
4. During any access to a utility bus peripheral in which its decode space has been disabled.
Upon a PCIRST#, this signal is driven inactive (high).
ECSADDR O
[2:0]
ENCODED CHIP SELECTS: ECSADDR[2:0] are the encoded chip selects and/or
control signals for the Utility Bus peripherals supported by the SIO/SIO.A. The
binary code formed by the three signals indicates which Utility Bus device is
selected. These signals tie to the address inputs of two external 74F138 decoder
chips and are driven valid/invalid from the SA[16:0] and LA[23:17] address lines.
Upon PCIRST#, these signals are driven high.
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