82378ZB Datasheet, PDF (42/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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3.1.15. IADRBE—ISA ADDRESS DECODER ROM BLOCK ENABLE REGISTER
Address Offset:
Default value:
Attribute:
49h
00h
Read/Write
ISA addresses within the enabled ranges result in the ISA memory cycle being forwarded to the PCI Bus. If the
memory block is disabled, the ISA cycle is not forwarded to the PCI Bus. For each bit, 1=Enable and 0=Disable.
Bit
Description
Bit
Description
7
880-896K Memory Enable
3
816-832K Memory Enable
6
864-880K Memory Enable
2
800-816K Memory Enable
5
848-864K Memory Enable
1
784-800K Memory Enable
4
832-848K Memory Enable
0
768-784K Memory Enable
3.1.16. IADBOH—ISA ADDRESS DECODER BOTTOM OF HOLE REGISTER
Address Offset:
Default value:
Attribute:
4Ah
10h
Read/Write
This register defines the bottom of the ISA Address Decoder hole. The hole is defined by the following equation:
TOH ≥ address ≥ BOH, where BOH is the bottom of the hole address programmed into this register and TOH is
the top of the hole address programmed into the IADTOH Register. ISA master or DMA addresses falling within
the hole will not be forwarded to the PCI Bus. The hole can be sized in 64-Kbyte increments and placed
anywhere between 1 Mbyte and 16 Mbytes on any 64-Kbyte boundary. When TOH < BOH, the hole is
effectively disabled. The default value for the BOH and TOH disables the hole.
For example, to program the BOH at 1 Mbyte, this register should be set to 10h. To program the BOH at
2 Mbytes, this register should be set to 20h. To program the BOH at 8 Mbytes, this register should be set to 80h.
Bit
Description
7:0
ISA Bottom of Memory Hole Address: Bits[7:0] correspond to address lines A[23:16], respectively.
3.1.17. IADTOH—ISA ADDRESS DECODER TOP OF HOLE REGISTER
Address Offset:
Default value:
Attribute:
4Bh
0Fh
Read/Write
This register defines the top of the ISA Address Decoder hole. The hole is defined by the following equation:
TOH ≥ address ≥ BOH, where BOH is the bottom of the hole address programmed into the LADBOH Register
and TOH is the top of the hole address programmed into this Register. ISA master or DMA addresses within the
hole will not be forwarded to the PCI Bus. The hole can be sized in 64-Kbyte increments and placed anywhere
between 1 Mbyte and 16 Mbytes on any 64-Kbyte boundary. When TOH < BOH, the hole is disabled. The
default value for the BOH and TOH disables the hole.
For example, to program the TOH at 1 Mbyte + 64 Kbytes, this register should be set to 10h. To program the
TOH at 2 Mbytes + 128 Kbytes, this register should be set to 21h. To program the TOH at 12 Mbytes, this
register should be set to BFh.
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