82378ZB Datasheet, PDF (103/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
Processor
Register
Access
INT, NMI
INIT, SMI
Local APIC
APIC Bus
Processor
Local APIC
SIO.A
I/O APIC
057106
Figure 6. APIC System Structure
The 82379AB I/O APIC Unit consists of a set of interrupt input signals, a 16-entry Interrupt Redirection Table,
programmable registers, and a message unit for sending and receiving APIC messages over the APIC Bus
(Figure 7). I/O devices inject interrupts into the system by asserting one of the interrupt lines to the I/O APIC
(Figure 8). The I/O APIC selects the corresponding entry in the Redirection Table and uses the information in
that entry to format an interrupt request message. Each entry in the Redirection Table can be individually
programmed to indicate edge/level sensitive interrupt signals, the interrupt vector and priority, the destination
processor, and how the processor is selected (statically or dynamically). The information in the table is used to
transmit a message to other APIC units (via the APIC Bus).
The 82379AB I/O APIC contains a set of programmable registers. Two of the registers (I/O Register Select and
I/O Window Registers) are located in the CPU's memory space and are used to indirectly access the other APIC
registers as described in the Register Description section. The Version Register provides the implementation
version of the I/O APIC. The I/O APIC ID Register is programmed with an ID value that serves as a physical
name of the I/O APIC. This ID is loaded into the ARB ID Register when the I/O APIC ID Register is written and is
used during bus arbitration.
NOTE
1. When the 82379AB I/O APIC receives an interrupt request, the 82379AB flushes its buffers and
requests all system buffers pointing to PCI to be flushed (via the FLSHREQ#/MEMREQ# signals).
The APIC does not send the interrupt message over the APIC Bus until the 82379AB receives
confirmation (via the MEMACK# signal) that all buffers have been flushed and temporarily
disabled.
2. The interrupt number or the vector does not imply a particular priority for being sent. The I/O APIC
continually polls the 16 interrupts in a rotating fashion, one at a time. The pending interrupt polled
first is the one sent.
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