82378ZB Datasheet, PDF (4/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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3.1.23. MAR2—MEMCS# ATTRIBUTE REGISTER #2 ................................ ................................ ............. 47
3.1.24. MAR3—MEMCS# ATTRIBUTE REGISTER #3 ................................ ................................ ............. 48
3.1.25. PIRQ[3:0]#—PIRQ ROUTE CONTROL REGISTERS ................................ ................................ ...48
3.1.26. PACC—PIC/APIC CONFIGURATION CONTROL REGISTER (82379AB Only) ........................ 49
3.1.27. APICBASE—APIC BASE ADDRESS RELOCATION (82379AB Only) ................................ ....... 49
3.1.28. BIOS TIMER BASE ADDRESS REGISTER ................................ ................................ .................. 50
3.1.29. SMICNTL—SMI CONTROL REGISTER ................................ ................................ ........................ 50
3.1.30. SMIEN—SMI ENABLE REGISTER ................................ ................................ ................................ 51
3.1.31. SEE—SYSTEM EVENT ENABLE REGISTER ................................ ................................ .............. 51
3.1.32. FTMR—FAST OFF TIMER REGISTER ................................ ................................ ......................... 52
3.1.33. SMIREQ—SMI REQUEST REGISTER ................................ ................................ .......................... 53
3.1.34. CTLTMR—CLOCK SCALE STPCLK# LOW TIMER ................................ ................................ .....54
3.1.35. CTLTMRH—CLOCK SCALE STPCLK# HIGH TIMER ................................ ................................ .54
3.2. DMA REGISTER DESCRIPTION ................................ ................................ ................................ ............. 55
3.2.1. DCOM—DMA COMMAND REGISTER ................................ ................................ ............................ 55
3.2.2. DCM—DMA CHANNEL MODE REGISTER ................................ ................................ .................... 55
3.2.3. DCEM—DMA CHANNEL EXTENDED MODE REGISTER (82378ZB Only) ................................ 56
3.2.4. DR—DMA REQUEST REGISTER ................................ ................................ ................................ ....59
3.2.5. MASK REGISTER—WRITE SINGLE MASK BIT ................................ ................................ ............. 59
3.2.6. MASK REGISTER—WRITE ALL MASK BITS ................................ ................................ ................. 60
3.2.7. DS—DMA STATUS REGISTER ................................ ................................ ................................ ....... 60
3.2.8. DMA BASE AND CURRENT ADDRESS REGISTERS (8237 COMPATIBLE SEGMENT) ......... 61
3.2.9. DMA BASE AND CURRENT BYTE/WORD COUNT REGISTERS (8237 COMPATIBLE
SEGMENT) ................................ ................................ ................................ ................................ ................ 61
3.2.10. DMA MEMORY BASE LOW PAGE AND CURRENT LOW PAGE REGISTERS ....................... 62
3.2.11. DMA MEMORY BASE HIGH PAGE AND CURRENT HIGH PAGE REGISTERS ...................... 62
3.2.12. DMA CLEAR BYTE POINTER REGISTER ................................ ................................ .................... 63
3.2.13. DMC—DMA MASTER CLEAR REGISTER ................................ ................................ ................... 64
3.2.14. DCM—DMA CLEAR MASK REGISTER ................................ ................................ ........................ 64
3.2.15. SCATTER/GATHER (S/G) COMMAND REGISTER (82378ZB Only) ................................ ......... 64
3.2.16. SCATTER/GATHER (S/G) STATUS REGISTER (82378ZB Only) ................................ .............. 65
3.2.17. SCATTER/GATHER (S/G) DESCRIPTOR TABLE POINTER REGISTER (82378ZB Only) .....67
3.2.18. SCATTER/GATHER (S/G) INTERRUPT STATUS REGISTER (82378ZB Only) ....................... 67
3.3. TIMER REGISTER DESCRIPTION ................................ ................................ ................................ ......... 68
3.3.1. TCW—TIMER CONTROL WORD REGISTER ................................ ................................ ................ 68
3.3.2. INTERVAL TIMER STATUS BYTE FORMAT REGISTER ................................ ............................. 70
3.3.3. COUNTER ACCESS PORTS REGISTER ................................ ................................ ....................... 71
3.3.4. BIOS TIMER REGISTER ................................ ................................ ................................ ................... 71
3.4. INTERRUPT CONTROLLER REGISTER DESCRIPTION ................................ ................................ ....72
3.4.1. ICW1—INITIALIZATION COMMAND WORD 1 REGISTER ................................ ........................... 72
3.4.2. ICW2—INITIALIZATION COMMAND WORD 2 REGISTER ................................ ........................... 73
3.4.3. ICW3—INITIALIZATION COMMAND WORD 3 REGISTER ................................ ........................... 73
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