82378ZB Datasheet, PDF (78/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
3.5.2. NMI ENABLE AND REAL-TIME CLOCK ADDRESS REGISTER
Address Offset:
Default Value:
Attribute:
070h
Bit[6:0]=undefined, Bit 7=1
Write Only
The Mask Register for the NMI interrupt is at I/O address 070h shown below. The most significant bit enables or
disables all NMI sources including IOCHK# and the NMI Port. Write an 80h to Port 70h to mask the NMI signal.
This port is shared with the real-time clock. The real-time-clock uses the lower six bits of this port to address
memory locations. Writing to Port 70h sets both the enable/disable bit and the memory address pointer. Do not
modify the contents of this register without considering the effects on the state of the other bits. Reads and
writes to this register address flow through to the ISA Bus.
Bit
Description
7 NMI Enable: 1=Disable; 0=Enable.
6:0 Real Time Clock Address: Used by the Real Time Clock on the Base I/O component to address
memory locations. Not used for NMI enabling/disabling.
3.5.3. PORT 92 REGISTER
Address Offset:
Default Value:
Attribute:
92h
24h
Read/Write
This register is used to support the alternate reset (ALT_RST#) and alternate A20 (ALT_A20) functions. This
register is only accessible if bit 6 in the Utility Bus Chip Select B Register is set to a 1. Reads and writes to this
register location flow through to the ISA Bus.
Bit
Description
7:6 Reserved: Read as 0s.
5 Reserved: Read as 1.
4:3 Reserved: Read as 0s.
2 Reserved: Read as 1.
1 ALT_A20 Signal Control—R/W: 0=ALT_A20 signal negated (low). 1=ALT_A20 signal asserted (high).
0 Alternate System Reset—R/W: This read/write bit provides an alternate system reset function. This
function provides an alternate means to reset the system CPU to effect a mode switch from Protected
Virtual Address Mode to the Real Address Mode. This provides a faster means of reset than is provided
by the Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the
ALT_RST# signal to pulse active (low) for approximately 4 SYSCLK's. Before another ALT_RST# pulse
can be generated, this bit must be written back to a 0.
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