82378ZB Datasheet, PDF (96/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
The S/G Command and Status Registers are used to control the operational aspect of S/G transfers. The SGD
Table Pointer Register holds the address of the next buffer descriptor in the SGD Table.
The next buffer descriptor is fetched from the SGD Table by a DMA read transfer. DACK# will not be asserted
for this transfer because the IO device is the SIO itself. The SIO will fetch the next buffer descriptor from either
PCI memory or ISA memory, depending on where the SGD Table is located. If the SGD table is located in PCI
memory, the memory read will use the line buffer to temporarily store the PCI read before loading it into the DMA
S/G registers. The line buffer mode (8-byte or single transaction) for the S/G fetch operation will be the same as
what is set for all DMA operations. If set in 8-byte mode, the SGD Table fetches will be PCI burst memory reads.
The SGD Table PCI cycle fetches are subject to all types of PCI cycle termination (retry, disconnect, target-
abort, master-abort). The fetched SGD Table data is subject to normal line buffer coherency management and
invalidation. EOP will be asserted at the end of the complete link transfer.
To initiate a typical DMA S/G transfer between memory and an I/O device, the following steps are required:
1. Software prepares a SGD Table in system memory. Each SGD is 8 bytes long and consists of an address
pointer to the starting address and the transfer count of the memory buffer to be transferred. In any given
SGD Table, two consecutive SGDs are offset by 8 bytes and are aligned on a 4-byte boundary.
Each S/G Descriptor for the linked list contains the following information:
a. Memory Address (buffer start) 4 bytes
b. Transfer Size (buffer size)
2 bytes
c. End of Link List
1 bit ( MSB)
Dword 0
byte 3
Dword 1 EOL RSVD
byte 2
byte 1
Mem ory Address
byte 0
RSVD
Transfer Size
Address
XXX0h
XXX3h
XXX4h
XXX7h
Figure 3. SGD Format
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2. Initialize the DMA Channel Mode and DMA Channel Extended Mode Registers with transfer specific
information like 8/16-bit I/O device, Transfer Mode, Transfer Type, etc.
3. Software provides the starting address of the SGD Table by loading the SGD Table Pointer Register.
4. Engage the S/G function by writing a Start command to the S/G Command Register.
5. The Mask register should be cleared as the last step of programming the DMA register set. This is to prevent
the DMA from starting a transfer with a partially loaded command description.
6. Once the register set is loaded and the channel is unmasked, the DMA will generate an internal request to
fetch the first buffer from the SGD Table.
After the above steps are finished, the DMA will then respond to DREQ or software requests. The first transfer
from the first buffer moves the memory address and word count from the Base register set to the Current
register set. As long as S/G is active and the Base register set is not loaded and the last buffer has not been
fetched, the channel will generate a request to fetch a reserve buffer into the Base register set. The reserve
buffer is loaded to minimize latency problems going from one buffer to another. Fetching a reserve buffer has a
lower priority than completing DMA transfers for the channel.
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