82378ZB Datasheet, PDF (63/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
for 8-bit channels or 128 Kbyte boundary for 16-bit channels. This is extended address mode. In this mode, the
ISA Bus controller generates the signals MEMR# and MEMW# only for addresses below 16 Mbytes.
For the 82378ZB in S/G, these registers store the 8 bits from the highest byte of the current memory address.
During a S/G transfer, the DMA will load a reserve buffer into the base memory address register.
82378ZB:
Bit
Description
7:0 DMA High Page and Base High Page [31:24]. These bits represent the eight most-significant
address bits when forming the full 32-bit address for a DMA transfer. Upon PCIRST# or Master Clear,
the value of these bits is 00h.
82379AB:
Bit
Description
7:3 Reserved.
2:0 DMA High Page and Base High Page [26:24]. These bits represent the three most-significant
address bits when forming the full 27-bit address for a DMA transfer. Upon PCIRST# or Master Clear,
the value of these bits is 00h.
3.2.12. DMA CLEAR BYTE POINTER REGISTER
Address Offset:
Default Value:
Attribute:
Channels 0−3—00Ch; Channels 4−7—0D8h
All bits undefined
Write Only
Writing to this register executes the clear byte pointer command. This command is executed prior to writing or
reading new address or word count information to the DMA. This command initializes the byte pointer flip-flop to
a known state so that subsequent accesses to register contents will address upper and lower bytes in the
correct sequence.
The Master Clear command clears the internal latch used to address the upper or lower byte of the 16-bit
Address and Word Count Register. The Host CPU may read or write a 16-bit DMA controller register by
performing two consecutive accesses to the I/O port. The Clear Byte Pointer command precedes the first
access. The first I/O write to a register port loads the least significant byte, and the second access automatically
accesses the most significant byte.
Bit
Description
7:0 Clear Byte Pointer: No specific pattern. Command enabled with a write to the I/O port address.
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