82378ZB Datasheet, PDF (16/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
Signal Name Type
Description
MEMREQ# t/s/o
MEMORY REQUEST: If the SIO/SIO.A is configured in Guaranteed Access Time
(GAT) Mode, MEMREQ# will be asserted when an ISA master or DMA is
requesting the ISA Bus (along with FLSHREQ#) to indicate that the SIO/SIO.A
requires ownership of the main memory. MEMREQ# is tri-stated from the leading
edge of PCIRST#. MEMREQ# remains tri-stated until driven by the SIO/SIO.A.
After PCIRST, MEMREQ# is driven inactive asynchronously from PCIRST#
inactive. The SIO/SIO.A asserts FLSHREQ# concurrently with asserting
MEMREQ#.
FLSHREQ# MEMREQ# Meaning
FLSHREQ# t/s/o
1
1
Idle
0
1
Flush buffers pointing towards PCI to
avoid ISA deadlock
1
0
82378ZB. Reserved
82379AB. GAT enabled or disabled: For buffer
coherency in APIC systems, the buffers
pointing to main memory must be flushed
and disabled for the duration of assertion.
0
0
GAT mode. Guarantee PCI Bus immediate
access to main memory (this may or may
not require the PCI-to-main memory
buffers to be flushed first depending on
the number of buffers).
FLUSH REQUEST: FLSHREQ# is generated by the SIO/SIO.A to command all of
the system's posted write buffers pointing towards the PCI Bus to be flushed. This is
required before granting the ISA Bus to an ISA master or the DMA. FLSHREQ# is
tri-stated from the leading edge of PCIRST#. FLSHREQ# remains tri-stated until
driven by the SIO/SIO.A. After PCIRST, FLSHREQ# is driven inactive
asynchronously from PCIRST# inactive.
MEMACK# I
MEMORY ACKNOWLEDGE: MEMACK# is the response handshake that indicates
to the SIO/SIO.A that the function requested over the MEMREQ# and/or
FLSHREQ# signals has been completed. In GAT mode (MEMREQ# and
FLSHREQ# asserted), the main memory bus is dedicated to the PCI Bus and the
system's posted write buffers pointing towards the PCI Bus have been flushed and
are disabled. In non-GAT mode (FLSHREQ# asserted alone), this means the
system's posted write buffers have been flushed and are disabled. In either case,
the SIO/SIO.A can now grant the ISA Bus to the requester.
2.3. Address Decoder Signal
Signal Name Type
Description
MEMCS#
O
MEMORY CHIP SELECT. MEMCS# is a programmable address decode signal
provided to a Host CPU bridge. A CPU bridge can use MEMCS# to forward a PCI
cycle to main memory behind the bridge. MEMCS# is driven one PCI clock after
FRAME# is sampled active (address phase) and is valid for one clock cycle before
going inactive. MEMCS# is high upon reset.
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