82378ZB Datasheet, PDF (33/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
3.1.2. DID—DEVICE IDENTIFICATION REGISTER
Address Offset:
Default Value:
Attribute:
02–03h
0484h
Read Only
The DID Register contains the device identification number. This register, along with the Vendor ID, uniquely
identifies the SIO/SIO.A. Writes to this register have no effect.
Bit
Description
15:0 Device Identification Number: This is a 16-bit value assigned to the SIO/SIO.A.
3.1.3. COM—COMMAND REGISTER
Address Offset:
Default Value:
Attribute:
04–05h
0007h
Read/Write
Bit
Description
15:5 Reserved: Read as 0.
4 PMWE (Postable Memory Write Enable): Enable postable memory write, memory write and
invalidate, and memory read pre-fetch commands. The SIO/SIO.A does not support these commands
as a master or slave so this bit is not implemented. This bit will always be read as a 0.
3 SCE (Special Cycle Enable): 1=Enable (the SIO/SIO.A will recognize PCI Special Cycles); 0=Disable
(the SIO/SIO.A will ignore all PCI special cycles). This bit MUST be enabled if the STPCLK feature is
being used.
2 BME (Bus Master Enable): Since the SIO/SIO.A always requests the PCI Bus on behalf of ISA
masters, DMA, or line buffer PCI requests, this bit is hardwired to a 1 and will always be read as a 1.
1 MSE (Memory Space Enable): Enables SIO/SIO.A to accept a PCI-originated memory cycle. Since
the SIO/SIO.A always responds to PCI-originated memory cycles (and ISA-bound cycles) by asserting
DEVSEL#, this bit is hardwired to a 1 and will always be read as a 1.
0 IOSE (I/O Space Enable): Enable SIO/SIO.A to accept a PCI-originated I/O cycle. Since the
SIO/SIO.A always responds to a master I/O cycle, this bit is hardwired to a 1 and will always be read as
a 1.
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