82378ZB Datasheet, PDF (51/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
Bit
Description
0 SMI# Gate (CSMIGATE)—R/W: When bit 0=1, the SMI# signal is enabled and a system management
interrupt condition causes the SMI# signal to be asserted. When bit 0=0 (default), the SMI# signal is
masked and negated. This bit only affects the SMI# signal and does not affect the detection/recording
of SMI events (i.e., This bit does not affect the SMI status bits in the SMIREQ Register). Thus, SMI
conditions can be pending when this bit is set to 1. If an SMI is pending when this bit is set to 1, the
SMI# signal is asserted.
3.1.30. SMIEN—SMI ENABLE REGISTER
Address Offset:
Default Value:
Attribute:
A2−A3h
0000h
Read/Write
This register enables the generation of SMI (asserting the SMI# signal) for the associated hardware events
(bits[5:0]), and software events (bit 7). When a hardware event is enabled, the occurrence of a corresponding
event results in the assertion of SMI#, if enabled via the SMICNTL Register. The SMI# is asserted independent
of the current power state (Power-On or Fast-Off). The default for all sources in this register is disabled.
Bit
Description
15:8 Reserved.
7 APMC Write SMI Enable: 1=Enable; 0=Disable
6 EXTSMI# SMI Enable: 1=Enable; 0=Disable
5 Fast-Off Timer SMI Enable: 1=Enable; 0=Disable
4 IRQ12 SMI Enable (PS/2 Mouse Interrupt): 1=Enable; 0=Disable
3 IRQ8 SMI Enable (RTC Alarm Interrupt): 1=Enable; 0=Disable
2 IRQ4 SMI Enable (COM2/COM4 Interrupt or Mouse): 1=Enable; 0=Disable
1 IRQ3 SMI Enable (COM1/COM3 Interrupt or Mouse): 1=Enable; 0=Disable
0 IRQ1 SMI Enable (Keyboard Interrupt): 1=Enable; 0=Disable
3.1.31. SEE—SYSTEM EVENT ENABLE REGISTER
Address Offsset:
Default Value:
Attribute:
A4−A7h
00000000h
Read/Write
This register enables hardware events as system events or break events for power management control. For I/O
locations that can cause a system event via bits[27:24], refer to the Power Management section.
System events: Activity by these events can keep the system from powering down. When a system event is
enabled, the corresponding hardware event activity prevents a Fast-Off powerdown condition. Anytime the
corresponding hardware event occurs (signal is asserted or an access within the defined range), the Fast-Off
Timer is re-loaded with its initial count.
Break events: These events can awaken a powered down system. When a break event is enabled, the
corresponding hardware event activity powers up the system by negating STPCLK#. Note that STPCLK# is not
51