82378ZB Datasheet, PDF (107/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
4.9.4. PULSING OF APICD1 DURING CPU RESET (82379AB Only)
For dual-processing (DP) ISA systems using the Pentium® processor at ICOMP index 735\90 (or 815\100) and
the A-1 stepping of the 82434NX PCMC host bridge an anomily can occur when the IOAPIC data line is pulsed
during CPU reset. (Single processor designs are not affected. Also, Pentium Pro processor systems are not
affected.) To avoid this issue, use one of the following workarounds:
The CPUs APIC data lines (APICD[0,1]), have secondary functions when CPU RESET (CPURST) is active.
APICD1 is the APICEN (APIC enable) pin and APICD0 is the DPEN# (dual processor enable) pin. The local
APICs are enabled if APICEN is sampled active high on the falling edge of CPURST. Also, during RESET, the
second CPU drives DPEN# active low to indicate to the boot processor that it is present.
On the A-1 stepping of the 82434NX PCMC, there is approximately a 1-ms delay (specifically 66,672 external
host clocks) between the negation of PCIRST# and the negation of CPURST following a cold system boot (i.e.,
the PWROK input of the PCMC transitions from low to high). During this 1-ms window, the I/O APIC in the
SIO.A, which is no longer in reset, begins to monitor the APIC Bus for valid messages. APICEN (APICD1 = logic
1) and DPEN# (APICD0 = logic 0) remain asserted during this period. The I/O APIC interprets the states of
these two bits as the beginning of a normal APIC message and continues to sample the APIC data lines. The I/O
APIC responds, per the APIC protocol, by driving APICD1(APICEN) low once every 20 APICCLKs, indicating a
checksum error has been detected on the current message. Under these circumstances, this is proper operation
for the SIO.A.
From the time that PCIRST# negates until the time that CPURST negates, the I/O APIC periodically pulses
APICD1 low for one out of every 20 APICCLKs. If the pulse on APICD1 (APICEN) aligns with the falling edge of
CPU RESET (CPURST), the local APICs will not be enabled; this prevents proper DP or DP-ready functionality
(Figure 10}.
66,672 Hz
CPURST
PCIRST#
APICD1
APICCLK
057110
Figure 10. RESET/APIC Data Signl Timing (Not To Scale)
Hardware Solution #1:
Calculate the window for the APICD1 pulse relative to CPURST for a given host clock (HCLK) and APIC Clock
(APICCLK) frequency. The following example demonstrates that by using a 60.0 MHz HCLK and a 15.0 MHz
APICCLK (0.01% accuracy for both) the APICD1 pulse will be outside the sampling window of CPURST. With
these equations, equally acceptable windows can be found for other values of HCLK and APICCLK.
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