82378ZB Datasheet, PDF (120/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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82379AB, if the wait for stop grant special cycle function is disabled, the SIO.A does not wait for the stop
grant special cycle before starting the timer. Note, also, that a break event also negates STPCLK#. This
feature is not programmable in the 82378ZB.
NOTE
If STPCLK# is negated and a break event occurs, the STPCLK# Timer is loaded with the value in the
CTLTMRH Register.
4.11.5. DUAL-PROCESSOR POWER MANAGEMENT SUPPORT (82379AB Only)
Figure 18 depicts the power management support for dual-processor (DP) or P54CT upgrade processor
configuration. The input signals of SMI#, STPCLK#, and NMI of both OEM and upgrade sockets are tied
together.
Local
Interrupts
P54C
P54CM/CT
Local
APIC
STPCLK#
SMI#
NMI
APIC Bus
System I/O
Interrupts
STPCLK#
SMI#
NMI
I/O APIC
Local
APIC
Local
Interrupts
8259A _SIO.A
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Figure 18. SIO.A Dual Processor System Configuration
4.11.5.1. SMI# Delivery Mechanism
For Uni or CT upgrade processor system configuration, SMI# can either be delivered through the SIO.A SMI#
signal or I/O APIC. For the P54C/CM Dual-processor configuration, SMI# should be deliver through I/O APIC
only. Ideally, the OS will put the CM processor in Autohalt after the CM processor received a Fast-Off SMI#. The
CM processor will wake up if any non-masked system events occur.
4.11.5.2. STPCLK# Tied to Both Sockets
To support a glueless upgrade socket, it is necessary to tie STPCLK# to both sockets. For P54C/CT processor
configuration, the P54CT processor will disable P54C and the toggling of STPCLK# has no effect to P54C. For a
P54C/CM DP configuration, the toggling of STPCLK# effects both processors (unless the processor is in
Autohalt state). Both processors respond with a STPGNT special bus cycle after recognizing STPCLK# low.
Both of the STPGNT special bus cycles are passed onto PCI by the PCMC as PCI STPGNT special cycles.
When bit 6=0 in the SMICNTL Register, the SIO.A recognizes the first STPGNT# assertion and negates
STPCLK# upon the Stop Clock timer expiration or a stop break event.
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