82378ZB Datasheet, PDF (14/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
Signal Name Type
Description
DEVSEL#
I/O
(s/t/s)
DEVICE SELECT: The SIO/SIO.A asserts DEVSEL# to claim a PCI transaction
through positive or subtractive decoding. DEVSEL# is tri-stated from the leading
edge of PCIRST#. DEVSEL# remains tri-stated until driven by the SIO/SIO.A as
either a master or a slave.
PIRQ[3:0]# I
PCI INTERRUPT REQUEST: PIRQ#s are used to generate asynchronous
interrupts to the CPU via the Programmable Interrupt Controllers (82C59s)
integrated in the SIO/SIO.A. These signals are defined as level sensitive and are
asserted low. The PIRQx# interrupts can be steered into any unused IRQ interrupt.
The PIRQx# Route Control Register determines which IRQ interrupt each PCI
interrupt is steered into. These pins include a weak internal pull-up resistor.
PAR
O
CALCULATED PARITY SIGNAL: A single parity bit is provided over AD[31:0] and
C/BE[3:0]. PAR is always driven low by the 82379AB synchronously from the
leading edge of PCIRST#.
SERR#
I
SYSTEM ERROR: SERR# can be pulsed active by any PCI device that detects a
system error condition. Upon sampling SERR# active, the SIO/SIO.A generates a
non-maskable interrupt (NMI) to the CPU.
2.2. PCI Arbiter Signals
Signal Name Type
Description
CPUREQ# I
CPU REQUEST: This signal provides the following functions:
1. If CPUREQ# is sampled high on the trailing edge of PCIRST#, the internal arbiter
is enabled. If CPUREQ# is sampled low on the trailing edge of PCIRST#, the
internal arbiter is disabled. This requires that the host bridge drive CPUREQ# high
during PCIRST#.
2. If the SIO/SIO.A internal arbiter is enabled, this pin is configured as CPUREQ#.
An active low assertion indicates that the CPU initiator desires the use of the PCI
Bus. If the internal arbiter is disabled, this pin is meaningless after reset.
This pin has a weak internal pull-up resistor.
REQ0#/
I
SIOGNT#
REQUEST 0/SIO GRANT: If the SIO/SIO.A internal arbiter is enabled, this pin is
configured as REQ0#. An active low assertion indicates that Initiator0 desires the
use of the PCI Bus. If the internal arbiter is disabled, this pin is configured as
SIOGNT#. When asserted, SIOGNT# indicates that the external PCI arbiter has
granted use of the bus to the SIO/SIO.A. This pin has a weak internal pull-up
resistor.
REQ1#
I
REQUEST 1: If the SIO/SIO.A internal arbiter is enabled through the Arbiter
Configuration Register, then this signal is configured as REQ1#. An active low
assertion indicates that Initiator1 desires the use of the PCI Bus. If the internal
arbiter is disabled, the SIO/SIO.A ignores REQ1# after reset. This pin has a weak
internal pull-up resistor.
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