82378ZB Datasheet, PDF (95/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
4.5.1.1. Compatible Timing (82378ZB and 82379AB)
Compatible timing runs at 8 SYSCLKs during the repeated portion of a Block or Demand mode transfer.
4.5.1.2. Type "A" Timing (82378ZB)
Type "A" timing is provided to allow shorter cycles to PCI memory. Type "A" timing runs at 6 SYSCLKs
(720 ns/cycle) during the repeated portion of a block or demand mode transfer. This timing assumes an 8.33
MHz SYSCLK. Type "A" timing varies from compatible timing primarily in shortening the memory operation to the
minimum allowed by system memory. The I/O portion of the cycle (data setup on write, I/O read access time) is
the same as with compatible cycles. The actual active command time is shorter, but it is expected that the DMA
devices which provide the data access time or write data setup time should not require excess IOR# or IOW#
command active time. Because of this, most ISA DMA devices should be able to use type "A" timing.
4.5.1.3. Type "B" Timing (82378ZB)
Type "B" timing is provided for 8/16-bit ISA DMA devices which can accept faster I/O timing. Type "B" only
works with PCI memory. Type "B" timing runs at 5 SYSCLKs (600 ns/cycle) during the repeated portion of a
Block or Demand mode transfer. This timing assumes an 8.33 MHz SYSCLK. Type "B" timing requires faster
DMA slave devices than compatible timing in that the cycles are shortened so that the data setup time on I/O
write cycles is shortened and the I/O read access time is required to be faster. Some of the current ISA devices
should be able to support type "B" timing, but these will probably be more recent designs using relatively fast
technology.
4.5.1.4. Type "F" Timing (82378ZB)
Type "F" timing provides high performance DMA transfer capability. These transfers are mainly for fast I/O
devices (i.e., IDE devices). Type "F" timing runs at 3 SYSCLKs (360 ns/cycle) during the repeated portion of a
Block or Demand mode transfer.
4.5.1.5. DREQ And DACK# Latency Control (82378ZB and 82379AB)
The SIO/SIO.A DMA arbiter maintains a minimum DREQ to DACK# latency on DMA channels programmed to
operate in compatible timing mode. This is to support older devices such as the 8272A. The DREQs are delayed
by eight SYSCLKs prior to being seen by the arbiter logic. Software requests will not have this minimum request
to DACK# latency.
4.5.2. ISA REFRESH CYCLES (82378ZB and 82379AB)
Refresh cycles are generated by two sources: the refresh controller inside the SIO/SIO.A component or by ISA
Bus masters other than the SIO/SIO.A. The ISA Bus controller will enable the address lines SA[15:0] so that
when MEMR# goes active, the entire ISA system memory is refreshed at one time. Memory slaves on the ISA
Bus must not drive any data onto the data bus during the refresh cycle.
4.5.3. SCATTER/GATHER (S/G) DESCRIPTION (82378ZB)
Scatter/Gather (S/G) provides the capability of transferring multiple buffers between memory and I/O without
CPU intervention. In S/G, the DMA can read the memory address and word count from an array of buffer
descriptors, located in system memory (ISA or PCI), called the S/G Descriptor (SGD) Table. This allows the
DMA controller to sustain DMA transfers until all of the buffers in the SGD Table are transferred.
95