82378ZB Datasheet, PDF (128/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
7.2. Thermal Specifications
Parameter
θ _{Junction to Case}
θ _{Case to Ambient}
Table 12. 82378 QFP Package Thermal Characteristics
Thermal Resistance - °C/Watt
Air Flow Rate (Ft./Min)
0
200
6.6
6.6
6.6
36.6
27.4
24
E
400
8.0. TESTABILITY
The TEST and TESTO pins are used to test the SIO/SIO.A. During normal operations, the TEST pin must be
grounded. The test output TESTO may be left as a no-connect (NC).
8.1. Global Tri-State
The TEST pin and IRQ3 are used to provide a high-impedance tri-state test mode. When the following input
combination occurs, all outputs and bi-directional pins are tri-stated, with the exception of TESTO:
TEST =
'1'
IRQ3 =
'1'
The SIO/SIO.A must be reset after the bi-directional and output pins have been tri-stated in this manner.
8.2. Nand Tree
A NAND Tree is provided primarily for VIL/VIH testing. The NAND Tree is also useful for ATE at board level
testing. The NAND Tree allows the tester to test the solder connections for each individual signal pin.
The TEST pin, along with IRQ5 or IRQ6, activates the NAND Tree. All bi-directional pins, and certain pure output
pins using bi-directional buffers for performance reasons, are tri-stated when the following input combinations
occur:
TEST =
'1'
IRQ5 =
'1'
- or -
TEST =
'1'
IRQ6 =
'0'
The output pulse train is observed at the TESTO test output. Pure output pins are not included directly in the
NAND Tree. As noted in Section 8.3, each output can be expected to toggle after the corresponding node noted
next to the pin name toggles from a "1" to a "0".
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