82378ZB Datasheet, PDF (121/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
4.11.5.3. SMI#/INTR (APIC MODE)
When the APIC is used for interrupt delivery, additional considerations exist regarding ordering. If local interrupts
(LINT0/1) are used in APIC mode, then the system can not guarantee an ordering between the local interrupts
and any related SMI# events.
In DP mode, interrupts can generally be directed to a specific processor, which may not be the same processor
that the SMI# is directed. The IRQ blocking logic in the SIO.A still operates with APIC delivery mode. Thus, if an
IRQ is enabled to cause an SMI# event, it will be blocked until the CSMIGATE is cleared, regardless of where
the IRQ or SMI is to be directed by the APIC.
4.11.6. INTERRUPT LEVELS AND SYSTEM EVENT GENERATION IN POWER MANAGED SYSTEMS
(82378ZB Only)
The 82378ZB (SIO) can use the 14 IRQ input pins (IRQ[15,9,8,7:3,1]) to generate hardware system events in
PCI systems that support power management mode by programming the System Event Enable Register bits
[15:0], corresponding to the selected interrupt. Detection of these events causes the Fast-Off Timer to be re-
loaded with its initial count value and negate the STPCLK# pin. The SIO samples the enabled interrupts as level
sensitive, active high signals, for system event determination.
Most motherboard devices or ISA add-in cards using an interrupt drive the interrupt low when the interrupt is
inactive, and only drive the interrupt high when it needs to generate an interrupt to the CPU. These devices work
properly with the 82378ZB level sensitive logic.
PC-AT System Design Considerations
Devices or ISA add-in cards that float their interrupt line (i.e., a device that doe not drive its interrupt low
when inactive) may not be able to use the power management capabilities of the 82378ZB. Thus, it is
recommended that these devices not be used with the 82378ZB.
4.12. Design Considerations (82378ZB/82379AB)
4.12.1. Good Layout Practice
Incorrect board layout practices have shown that care must be taken to minimize ground bounce that could
generate noise glitches above the threshold on the following signalsEOP, BALE, NMI, INT, DEVSEL#,
RSTDRV, and DACK[7:0]. Care should be taken not to route these signals long distances and to ensure that
they are terminated properly. An additional good layout practice is to pull any affected signals to ground with a
capacitor (120 pF) at each receiver. For DEVSEL#, a 50 pF capacitor should be sufficient.
4.12.2. ASYNCHRONOUSLY SWITCHING SIGNALS
Good design practice should ensure that asynchronously switching signals should not be routed along
synchronous signals to minimize crosstalk. On the SIO/SIO.A, the following signals switch
asynchronouslyECSADDR[2:0], ECSEN#, MEM16#, MEMCS#, UBUSOE#, UBUSTR.
The IRQ lines are susceptible to cross coupled switching noise from these asynchronous signals. It is
recommended that the IRQ signals not be routed along these asynchronously switching signals. If an IRQ signal
is routed along these signals, capacitors should be used (100 pF) to decouple the switching from the IRQ input.
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