82378ZB Datasheet, PDF (43/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
Bit
Description
7:0 ISA Top of Memory Hole Address: Bits[7:0] correspond to address lines A[23:16], respectively.
3.1.18. ICRT—ISA CONTROLLER RECOVERY TIMER REGISTER
Address Offset:
Default Value:
Attribute:
4Ch
56h
Read/Write
The I/O recovery mechanism in the SIO/SIO.A is used to add additional recovery delay between PCI originated
8-bit and 16-bit I/O cycles to the ISA Bus. The SIO/SIO.A automatically forces a minimum delay of five
SYSCLKs between back-to-back 8- and 16-bit I/O cycles to the ISA Bus. The delay is measured from the rising
edge of the I/O command (IOR# or IOW#) to the falling edge of the next BALE. If a delay of greater than five
SYSCLKs is required, the ISA I/O Recovery Time Register can be programmed to increase the delay in
increments of SYSCLKs. Note that no additional delay is inserted for back-to-back I/O "sub cycles" generated as
a result of byte assembly or disassembly. This register defaults to 8- and 16-bit recovery enabled with two
clocks added to the standard I/O recovery.
Bit
Description
7
Reserved: Read as 0.
6
8-Bit I/O Recovery Enable: 1=Enable delay programmed via bits[5:3]; 0=Disable Delay.
5:3
8-Bit I/O Recovery Times: This 3-bit field defines the recovery times for 8-bit I/O. Programmable
delays between back-to-back 8-bit PCI cycles to ISA I/O slaves is shown in terms of ISA clock
cycles (SYSCLK) added to the five minimum. The selected delay programmed into this field is
enabled/disabled via bit 6 of this register.
Bit[5:3]
001
010
011
100
SYSCLK
Added
+1
+2
+3
+4
Total
SYSCLKs
6
7
8
9
Bit[5:3]
101
110
111
000
SYSCLK
Added
+5
+6
+7
+8
Total
SYSCLKs
10
11
12
13
2
16-Bit I/O Recovery Enable: 1=Enable delay programmed via bits[1:0]; 0=Disable Delay.
1:0
16-Bit I/O Recovery Times: This 2-bit field defines the recovery time for 16-bit I/O. Programmable
delays between back-to-back 16-bit PCI cycles to ISA I/O slaves is shown in terms of ISA clock
cycles (SYSCLK) added to the five minimum. The selected delay programmed into this field is
enabled/disabled via bit 2 of this register.
Bit[5:3]
01
10
SYSCLK
Added
+1
+2
Total
SYSCLKs
6
7
Bit[5:3]
11
00
SYSCLK
Added
+3
+4
Total
SYSCLKs
8
9
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