82378ZB Datasheet, PDF (94/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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Channel 0
Channel 1
Channel 2
Channel 3
DMA-1
Channel 4
Channel 5
Channel 6
Channel 7
DM A-2
Figure 2. Internal DMA Controller
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For the 82378ZB, the DMA supports programmable 8 and 16-bit device sizes per channel using ISA-compatible,
Type "A", Type "B", or Type "F" transfer timing. Each DMA channel defaults to the compatible settings for DMA
device size: channels [3:0] default to 8-bit, count-by-bytes transfers, and channels [7:5] default to 16-bit, count-
by-words (address shifted) transfers. The SIO provides the timing control and data size translation necessary for
the DMA transfer between the PCI and the ISA Bus. ISA-compatible is the default transfer timing. Full 32-bit
addressing is supported as an extension of the ISA-compatible specification.
For the 82379AB, the DMA supports 8/16-bit device size using ISA-compatible timings. Each DMA channel is
hardwired to the compatible settings for DMA device size—channels [3:0] are hardwired to 8-bit, count-by-bytes
transfers and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. The 82379AB
provides the timing control and data size translation necessary for the DMA transfer between the PCI and the
ISA Bus. Full 27-bit addressing is supported as an extension of the ISA-compatible specification
For both the 82378ZB and 82379AB, a DMA device (I/O device) is always on the ISA Bus, but the memory
referenced is located on either an ISA Bus device or in main memory. For compatible timing mode, the
SIO/SIO.A drives the MEMR# or MEMW# strobes if the address is less than 16 Mbytes (00000000−
00FFFFFFh). Note that the 82379AB always generates ISA-Compatible DMA memory cycles. The MEMR# and
MEMW# memory strobes are generated, regardless of whether the cycle is decoded for PCI or ISA memory.
The SMEMR# and SMEMW# is generated if the address is less than 1 Mbyte (00000000−000FFFFFh). To avoid
aliasing problems when the address is greater than 16 Mbytes (1000000–7FFFFFFh), the MEMR# or MEMW#
strobe is not generated.
For the 82378ZB, if the memory is decoded to be on the ISA Bus, the DMA cycle runs as a compatible cycle. If
the memory is decoded to be on the PCI Bus, the cycle can run as compatible, "A", "B", or "F" type. The ISA
controller does not drive a valid address for type "A", "B", and "F" DMA transfers on the ISA Bus. For type "A",
"B", and "F" timing mode DMA cycles, the SIO only generates the MEMR# or MEMW# strobe when the address
is decoded for ISA memory. When this occurs, the cycle converts to compatible mode timing.
For both the 82378ZB and 82379AB, the channels can be programmed for any of four transfer modes—single,
block, demand, or cascade. Each of the three active transfer modes (single, block, and demand), can perform
three different types of transfers (read, write, or verify). Note that memory-to-memory transfers are not supported
by the 82379AB. The DMA supports fixed and rotating channel priorities. The DMA controller also features
refresh address generation, and auto-initialization following a DMA termination.
4.5.1. DMA TIMINGS
ISA-Compatible timing is provided for DMA slave devices. For the 82378ZB, three additional timings are
provided for I/O slaves capable of running at faster speeds. These timings are referred to as Type "A", Type "B",
and Type "F".
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