82378ZB Datasheet, PDF (62/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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For the 82378AB in S/G mode, these registers store the 16 bits of the current Byte/Word count. During S/G
transfer, the DMA will load a reserve buffer into the base Byte/Word Count register.
Bit
Description
15:0 Base and Current Byte/Word Count: These bits represent the 16 byte/word count bits used when
counting down a DMA transfer. Upon PCIRST# or Master Clear, the value of these bits is 0000h.
3.2.10. DMA MEMORY BASE LOW PAGE AND CURRENT LOW PAGE REGISTERS
Address Offset:
Default Value:
DMA Channel 0087h; DMA Channel 508Bh
DMA Channel 1083h; DMA Channel 6089h
DMA Channel 2081h; DMA Channel 708Ah
DMA Channel 3082h;
All bits undefined
The DMA Memory Low Page Register contains the eight second most-significant bits of the address (32-bit
address for the 82378ZB and 27-bit address for the 82379AB). The register works in conjunction with the DMA
controller's High Page Register and Current Address Register to define the complete address for the DMA
channel. This register may be re-initialized by an autoinitialize back to its original value. Autoinitialize takes place
only after a TC or EOP.
For the 82378ZB in S/G, these registers store the 8 bits from the third byte of the current memory address.
During a Scater-Gather transfer, the DMA will load a reserve buffer into the base memory address register.
Bit
Description
7:0 DMA Low Page and Base Low Page [23:16]. These bits represent the eight second most significant
address bits when forming the full address for a DMA transfer. Upon PCIRST# or Master Clear, the
value of these bits is 00h.
3.2.11. DMA MEMORY BASE HIGH PAGE AND CURRENT HIGH PAGE REGISTERS
Address Offset:
Default Value:
DMA Channel 0—0487h;
DMA Channel 1—0483h;
DMA Channel 2—0481h;
DMA Channel 3—0482h;
All bits undefined
DMA Channel 5—048Bh
DMA Channel 6—0489h
DMA Channel 7—048Ah
This register works in conjunction with the DMA controller's Current Low Page Register and Current Address
Register to define the complete address for the DMA channels and corresponds to the Current Address Register
for each channel. This register may be autoinitialized back to its original value. Autoinitialize takes place only
after a TC or EOP.
For the 82378ZB, this register contains the eight most significant bits of the 32-bit address. For the 82379AB,
this register contains the three most significant bits of the 27-bit address.
This register is set to 0 during the programming of both the Current Low Page Register and the Current Address
Register. Thus, if this register is not programmed after the other address and Low Page Registers are
programmed, then its value is 00h. In this case, the DMA channel operates the same as an 82C37 (from an
addressing standpoint). This is the address compatibility mode.
If the high 8 bits (3-bits for the 82379AB) of the address are programmed after the other addresses, then the
channel modifies its operation to increment (or decrement) the entire 32-bit (27-bit for the 82379AB) address.
This is unlike the 82C37 "Page" register in the original PCs which could only increment to a 64 Kbyte boundary
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