82378ZB Datasheet, PDF (72/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
3.4. Interrupt Controller Register Description
The SIO/SIO.A contains an ISA compatible interrupt controller that incorporates the functionality of two 82C59
interrupt controllers. The interrupt registers control the operation of the interrupt controller and can be accessed
from the PCI Bus via PCI I/O space. In addition, some of the registers can be accessed from the ISA Bus via
ISA I/O space.
3.4.1. ICW1—INITIALIZATION COMMAND WORD 1 REGISTER
Register Location:
Default Value:
Attribute:
INT CNTRL-1—020h; INT CNTRL-2—0A0h
All bits undefined
Write Only
A write to Initialization Command Word 1 starts the interrupt controller initialization sequence. Addresses 020h
and 0A0h are referred to as the base addresses of CNTRL-1 and CNTRL-2, respectively. An I/O write to the
CNTRL-1 or CNTRL-2 base address with bit 4 equal to 1 is interpreted as ICW1. For SIO/SIO.A-based ISA
systems, three I/O writes to "base address + 1" must follow the ICW1. The first write to "base address + 1"
performs ICW2, the second write performs ICW3, and the third write performs ICW4.
ICW1 starts the initialization sequence during which the following automatically occur:
a. The edge sense circuit is reset. This means that following initialization, an interrupt request (IRQ) input must
make a low-to-high transition to generate an interrupt.
b. The Interrupt Mask Register is cleared.
c. IRQ7 input is assigned priority 7.
d. The slave mode address is set to 7.
e. Special Mask Mode is cleared and Status Read is set to IRR.
f. If IC4 was set to 0, then all functions selected by ICW4 are set to 0. However, ICW4 must be programmed in
the SIO/SIO.A implementation of this interrupt controller, and IC4 must be set to a 1.
Bit
Description
7:5 ICW/OCW Select: These bits should be 000 when programming the SIO/SIO.A.
4 ICW/OCW Select: Bit 4 must be a 1 to select ICW1. After the fixed initialization sequence to ICW1,
ICW2, ICW3, and ICW4, the controller base address is used to write to OCW2 and OCW3. Bit 4 is a 0
on writes to these registers. A 1 on this bit at any time will force the interrupt controller to interpret the
write as an ICW1. The controller will then expect to see ICW2, ICW3, and ICW4.
3 LTIM (Edge/Level Bank Select): This bit is ignored by the SIO/SIO.Aand is read as a 1.
2 ADI—WO: Ignored for the SIO/SIO.A.
1 SNGL (Single or Cascade): This bit must be programmed to a 0 to indicate that two interrupt
controllers are operating in cascade mode on the SIO/SIO.A.
0 IC4 (ICW4 Write Required): This bit must be set to a 1.
72