82378ZB Datasheet, PDF (84/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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high active), whether the interrupt is signaled as edges or levels, as well as the destination and delivery mode of
the interrupt. The information in the redirection table is used to translate the corresponding interrupt pin
information into an inter-APIC message.
For a signal on an edge-sensitive interrupt input pin to be recognized as a valid edge (and not a glitch), the input
level on the pin must remain asserted until the I/O APIC Unit broadcasts the corresponding message over the
APIC Bus and the message has been accepted by the destination(s) specified in the destination field. Only then
will the source APIC be able to recognize a new edge on that Interrupt Input pin. That new edge only results in a
new invocation of the handler if its acceptance by the destination APIC causes the Interrupt Request Register bit
to go from 0 to 1. (In other words, if the interrupt wasn't already pending at the destination.)
Bit
Description
63:56
Destination field—R/W: If the Destination Mode of this entry is Physical Mode (bit 11=0), bits[59:56]
contain an APIC ID. If Logical Mode is selected (bit 11=1), the Destination Field potentially defines a
set of processors. Bits[63:56] of the Destination Field specify the logical destination address.
55:17 Reserved
16
Interrupt Mask—R/W: When this bit is 1, the interrupt signal is masked. Edge-sensitive interrupts
signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending). Level-asserts or
negates occurring on a masked level-sensitive pin are also ignored and have no side effects.
Changing the mask bit from unmasked to masked after the interrupt is accepted by a local APIC has
no effect on that interrupt. This behavior is identical to the case where the device withdraws the
interrupt before that interrupt is posted to the processor. It is software's responsibility to handle the
case where the mask bit is set after the interrupt message has been accepted by a local APIC unit
but before the interrupt is dispensed to the processor. When this bit is 0, the interrupt is not masked.
An edge or level on an interrupt pin that is not masked results in the delivery of the interrupt to the
destination.
15
Trigger Mode—R/W: The trigger mode field indicates the type of signal on the interrupt pin that
triggers an interrupt. This bit is set to 1 for level sensitive and 0 for edge sensitive.
14
Remote IRR—RO: This bit is used for level triggered interrupts. Its meaning is undefined for edge
triggered interrupts. For level triggered interrupts, this bit is set to 1 when local APIC(s) accept the
level interrupt sent by the I/O APIC. The Remote IRR bit is set to 0 when an EOI message with a
matching interrupt vector is received from a local APIC.
13
Interrupt Input Pin Polarity (INTPOL)—R/W: This bit specifies the polarity of the interrupt signal. A
0 selects high active and a 1 selects low active.
12
Delivery Status (DELIVS)—RO: The Delivery Status bit contains the current status of the delivery
of this interrupt. Delivery Status is read-only and writes to this bit (as part of a 32 bit word) do not
affect this bit. When bit 12=0 (IDLE), there is currently no activity for this interrupt. When bit 12=1
(Send Pending), the interrupt has been injected. However, its delivery is temporarily held up due to
the APIC Bus being busy or the inability of the receiving APIC unit to accept that interrupt at that time.
11
Destination Mode (DESTMOD)—R/W: This field determines the interpretation of the Destination
field. When DESTMOD=0 (physical mode), a destination APIC is identified by its ID. Bits 56 through
59 of the Destination field specify the 4-bit APIC ID. When DESTMOD=1 (logical mode), destinations
are identified by matching on the logical destination under the control of the Destination Format
Register and Logical Destination Register in each Local APIC. Bits 56 through 63 (8 MSB) of the
Destination field specify the 8 bit APIC ID.
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