82378ZB Datasheet, PDF (69/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
Bit
Description
3:1 Counter Mode Selection: Bits[3:1] select one of six possible operating modes:
Bit[3:1]
000
001
X10
X11
100
101
Mode
0
1
2
3
4
5
Function
Out signal on end of count (=0)
Hardware retriggerable one-shot
Rate generator (divide by n counter)
Square wave output
Software triggered strobe
Hardware triggered strobe
0 Binary/BCD Countdown Select: 0=Binary countdown. The largest possible binary count is 2¹⁶.
1=Binary coded decimal (BCD) count is used. The largest BCD count allowed is 10⁴.
Read Back Command
The Read Back Command is used to determine the count value, programmed mode, and current states of the
OUT pin and Null count flag of the selected counter or counters. The Read Back Command is written to the
Timer Control Word Register which latches the current states of the above mentioned variables. The value of the
counter and its status may then be read by I/O access to the counter address. Note that the Timer Counter
Register bit definitions are different during the Read Back Command than for a normal Timer Counter Register
write.
Bit
Description
7:6 Read Back Command: When bits[7:6] are both 1, the Read Back Command is selected during a write
to the Timer Control Word Register. Following the Read Back Command, I/O reads from the selected
counter's I/O addresses produce the current latch status, the current latched count, or both if bits 4 and
5 are both 0.
5 Latch Count of Selected Counters: When bit 5=1, the current count value of the selected counters
will be latched. When bit 4=0, the status will not be latched.
4 Latch Status of Selected Counters: When bit 4=1, the status of the selected counters will be latched.
When bit 4=0, the status will not be latched.
3 Counter 2 Select: When bit 3=1, Counter 2 is selected for the latch command selected with bits 4 and
5. When bit 3=0, status and/or count will not be latched.
2 Counter 1 Select: When bit 2=1, Counter 1 is selected for the latch command selected with bits 4 and
5. When bit 2=0, status and/or count will not be latched.
1 Counter 0 Select: When bit 1=1, Counter 0 is selected for the latch command selected with bits 4 and
5. When bit 1=0, status and/or count will not be latched.
0 Reserved: Must be 0.
Counter Latch Command
The Counter Latch Command latches the current count value at the time the command is received. This
command is used to insure that the count read from the counter is accurate (particularly when reading a two-
byte count). The count value is then read from each counter's count register (via the Counter Ports Access Ports
Register). One, two or all three counters may be latched with one Counter Latch Command.
If a Counter is latched once and then later latched again before the count is read, the second Counter Latch
Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued.
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