82378ZB Datasheet, PDF (41/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
3.1.13. MCSTOM—MEMCS# TOP OF MEMORY REGISTER
Address Offset:
Default value:
Attribute:
47h
00h
Read/Write
This register determines MEMCS# top of memory boundary. The top of memory boundary ranges up to
512 Mbytes, in 2-Mbyte increments. This register is typically set to the top of main memory. Accesses ≥
2 Mbytes and ≤ top of memory boundary results in the assertion of the MEMCS# signal (unless the address
resides in the hole programmed by the MCSBOH and MCSTOH Registers). A value of 00h disables this
2 Mbyte-to-top memory region. A value of 00h assigns the top of memory to include 2 Mbyte - 1. A value of FFh
assigns the top of memory to include 512 Mbytes - 1.
Bit
Description
7:0 Top of Main Memory: Bits[7:0] correspond to address lines AD[28:21], respectively.
3.1.14. IADCON—ISA ADDRESS DECODER CONTROL REGISTER
Address Offset:
Default value:
Attribute:
48h
01h
Read/Write
This register enables the forwarding of ISA or DMA memory cycles to the PCI Bus. In addition, this register sets
the top of the "1 Mbyte to top of main memory" region.
Bit
Description
7:4 ISA Memory Cycle Forwarding To PCI: The top can be assigned in 1 Mbyte increments from
1 Mbyte up to 16 Mbytes. ISA master or DMA accesses within this region are forwarded to PCI unless
they are within the hole.
Bits[7:4]
0000
0001
0010
0011
0100
0101
0110
0111
Top of Memory
1 Mbyte
2 Mbytes
3 Mbytes
4 Mbytes
5 Mbytes
6 Mbytes
7 Mbytes
8 Mbytes
Bits[7:4]
1000
1001
1010
1011
1100
1101
1110
1111
Top of Memory
9 Mbytes
10 Mbytes
11 Mbytes
12 Mbytes
13 Mbytes
14 Mbytes
15 Mbytes
16 Mbytes
3:0 ISA and DMA Memory Cycle To PCI Bus Enables: The memory block is enabled by writing a 1 to
the corresponding bit position. Setting the bit to 0 disables the corresponding block. ISA or DMA
memory cycles to the enabled blocks result in the ISA cycle being forwarded to the PCI Bus. The
BIOSCS# enable bit (bit 6 in the UBCSA Register) for the 896K-960K region overrides the function of
bit 3 of this register. If the BIOSCS# bit is set to a 1, the ISA or DMA memory cycle is always contained
to ISA, regardless of the setting of bit 3 in this register. If the BIOSCS# bit is disabled, the cycle is
forwarded to the PCI Bus if bit 3 in this register is enabled.
Bit
Memory Block
Bit
0
0−512-Kbyte Memory
2
1
512−640-Kbyte Memory
3
Memory Block
640−768-Kbyte VGA Memory
896−960-Kbyte Low BIOS
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