82378ZB Datasheet, PDF (105/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
4.9.1. PHYSICAL CHARACTERISTICS OF APIC BUS (82379AB Only)
The APIC Bus is a 3-wire synchronous bus connecting all APICs (all I/O units and all local units). Two of these
wires are used for data transmission, and one wire is a clock. For bus arbitration, the APIC uses only one of the
data wires. The bus is logically a wire-OR and electrically an open-drain connection providing for both message
transmission and arbitration for lowest priority. All the values mentioned in the protocol description are logical
values (i.e., "Bus Driven" is logical 1 and "Bus Not Driven" is logical 0). The electrical values are 0 for logical one
and 1 for logical zero.
4.9.2. ARBITRATION FOR APIC BUS (82379AB Only)
The APIC uses one wire arbitration to win the bus ownership. A rotating priority scheme is used for arbitration.
The winner of the arbitration becomes the lowest priority agent and assumes an arbitration ID of 0. All other
agents, except the agent whose arbitration ID is 15, increment their arbitration IDs by one. The agent whose ID
was 15 takes the winner's arbitration ID and increments it by one. Arbitration IDs are changed (incremented or
assumed) only for messages that are transmitted successfully. For lowest priority messages, the arbitration ID is
updated before the final status cycle, which ultimately decides if the message is successful. A message is
transmitted successfully if no CS error or acceptance error is reported for that message.
An APIC agent can acquire the bus using two different priority schemes; normal, or EOI (End Of Interrupt). EOI
has the highest priority. EOI priority is used to send EOI messages for level interrupts from local APIC to the I/O
APIC. When an agent requests the bus with EOI priority, all others requesting the bus with normal priorities back
off.
A bus arbitration cycle starts by the agent driving a start cycle (bit 1=EOI, bit 0=1) on the APIC bus (Table 7). Bit
1=1 indicates "EOI" priority and bit 1=0 indicates normal priority. Bit 0 should be 1.
In cycles 2 through 5, the agent drives the arbitration ID on bit 1 of the bus. High-order ID bits are driven first with
successive cycles proceeding to the low bits of the ID. All arbitration losers in a given cycle drop off the bus,
using every subsequent cycle as a tie breaker for the previous cycle. When all arbitration cycles are completed,
there will be only one agent left driving the bus
Table 7. TT_APICBusArbBus Arbitration Cycles
Cycle Bit 1
Bit 0
1
EOI
1
0 1 = normal, 1 1 = EOI
2
ArbID3 0
Arbitration ID bits 3 through 0
3
ArbID2 0
4
ArbID1 0
5
ArbID0 0
4.9.3. INTR AND THE PENTIUM^® PROCESSOR’S "THROUGH LOCAL MODE" (82379AB Only)
The B-1 thru B-5 steppings of the Pentium® processor at ICOMP index 735\90 (or 815\100) have a stepping
publication information (10AP) when using the local APIC in Through Local Mode (virtual wire). The Pentium
stepping information provides software solutions that permit the customer to use the local APIC in Through Local
Mode. This section provides hardware solutions.
If a processor has its Local APIC setup in Through Local Mode (virtual wire), the 82379AB can potentially negate
and then reassert INT before the interrupt acknowledge cycle for the first interrupt completes. When this occurs,
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