82378ZB Datasheet, PDF (79/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
3.5.4. DIGITAL OUTPUT REGISTER
Address Offset:
Default Value:
Attribute:
03F2h (Primary), 0372h (Secondary)
Bit[7:4,2:0]=undefined, Bit 3=0
Write only
This register is used to prevent UBUSOE# from responding to DACK2# during a DMA read access to a floppy
controller on the ISA Bus. If a second floppy (residing on the ISA Bus) is using DACK2# in conjunction with a
floppy on the Utility Bus, this prevents the floppy on the Utility Bus and the Utility Bus transceiver from
responding to an access targeted for the floppy on the ISA Bus. This register is also located in the floppy
controller device. Reads and writes to this register location flow through to the ISA Bus.
Bit
Description
7:4 Not Used: These bits exist in the floppy controller.
3 DMA Enable: When this bit is a 1, the assertion of DACK# will result in UBUSOE# being asserted. If
this bit is 0, DACK2# has no effect on UBUSOE#. This port bit also exists on the floppy controller. This
bit defaults to disable (0).
2:0 Not Used: These bits exist in the floppy controller.
3.5.5. RESET UBUS IRQ1/IRQ12 REGISTER
Address Offset:
Default Value:
Attribute:
60h
N/A
Read only
This address location (60h) is used to clear the mouse and keyboard interrupt functions to the CPU. Reads to
this address are monitored by the SIO/SIO.A. When the mouse interrupt function is enabled (bit 4 of the ISA
Clock Divisor Register is 1), the mouse interrupt function is provided on the IRQ12/M input signal. In this mode,
a mouse interrupt generates an interrupt through IRQ12/M to the Host CPU. A read of 60h releases IRQ12. If bit
4=0 in the ISA Clock Divisor Register, a read of address 60h has no effect on IRQ12/M. Reads and writes to this
register flow through to the ISA Bus. For additional information, see the IRQ12/M description in Signal
Description section. A read of 60h always releases IRQ1, regardless of the setting of bit 4 in the ISA Clock
Divisor Register.
Bit
Description
7:0 Reset IRQ1/IRQ12: No specific pattern. A read of address 60h executes the command.
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