82378ZB Datasheet, PDF (80/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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3.5.6. COPROCESSOR ERROR REGISTER
Address Offset:
Default Value:
Attribute:
F0h
N/A
Write only
This address location (F0h) is used when the SIO/SIO.A is programmed for coprocessor error reporting (bit 5 of
the ISA Clock Divisor Register is 1). Writes to this address are monitored by the SIO/SIO.A. In this mode, the
SIO/SIO.A generates an interrupt (INT) to the CPU when it receives an error signal (FERR# asserted) from the
CPU's coprocessor. Writing address F0h, when FERR# is asserted, causes the SIO/SIO.A to assert IGNNE#
and negate IRQ13. IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted, writing to
address F0h does not effect IGNNE#. Reads and writes to this register flow through to the ISA Bus. For
additional information, see the IGNNE# description in the Signal Description section
Bit
Description
7:0 Reset IRQ12: No specific pattern. A write to address F0h executes the command.
3.5.7. ELCR—EDGE/LEVEL CONTROL REGISTER
Address Offset:
Default Value:
Attribute:
INT CNTRL-1—04D0h; INT CNTRL-2—04D1h
00h
Read/Write
The Edge/Level Control Register is used to set the interrupts to be triggered by either the signal edge or the logic
level. INT0, INT1, INT2, INT8, INT13 must be set to edge sensitive. After a reset, all the INT signals are set to
edge sensitive. Each IRQ that a PCI interrupt is steered into (see the PIRQ Route Control Register) must have
it's interrupt set to level sensitive.
Bit
7:0 Edge/Level Select: 0=Edge sensitive interrupt; 1=Level sensitive.
Bit
Port 04D0h
Port 04D1h
0
INT0*
INT8*
1
INT1*
INT9
2
INT2*
INT10
3
INT3
INT11
4
INT4
INT12
5
INT5
INT13*
6
INT6
INT14
7
INT7
INT15
* Must be 0 when written.
3.6. Power Management Registers
This section describes the two power management registers (APMS and APMC) that are located in normal I/O
space. These registers are accessed via the CPU or PCI Bus with 8 bit accesses. Note that the rest of the
power management registers are part of the SIO/SIO.A configuration registers.
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