82378ZB Datasheet, PDF (113/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
NOTES:
1. The encoded chip select signals for BIOSCS# will always be generated for accesses to the upper 64 Kbytes at the top of
1 Mbyte (F0000–FFFFFh) and its aliases at the top of the 4 Gbytes and 4 Gbytes - 1 Mbyte. Access to the lower 64 Kbytes
(E0000–EFFFFh) and its aliases at the top of 4 Gbytes and 4 Gbytes –1 Mbyte can be enabled or disabled through the
SIO/SIO.A. An additional 384 Kbytes of BIOS memory at the top of 4 Gbytes (FFFD0000–FFFDFFFFh) can be enabled for
BIOS use.
2. The primary and secondary locations are programmable through the SIO/SIO.A. Only one location range can be enabled at
any one time. The floppy and IDE share the same enable and disable bit (i.e., if the floppy is set for primary, the IDE is also
set for primary).
3. These signals can be used to select additional configuration RAM.
4. COM1 and COM2 address ranges can be programmed for either Port A (COMACS#) or Port B (COMBCS#).
5. Only one address range (LPT1, LPT2, or LPT3) can be programmed at any one time.
Port 92h Function
The SIO/SIO.A integrates the Port 92h Register. This register provides the alternate reset (ALTRST) and
alternate A20 (ALT_A20) functions. Figure 14 shows how these functions are tied into the system.
DSKCHG Function
DSKCHG is tied directly to the DSKCHG signal of the floppy controller. This signal is inverted and driven onto
system data line 7 (SD7) during I/O read cycles to floppy address locations 3F7h (primary) or 377 (secondary)
as indicated by Table 9.
FLOPPYCS# Decode
Table 9. DSKCHG Summary Table
IDECSx# Decode
State of SD7 (Output)
State of UBUSOE#
Enabled
Enabled
Tri-stated
Enabled
Enabled
Disabled
Driven via DSKCHG
Disabled
Disabled
Enabled
Tri-stated
Enabled¹
Disabled
Disabled
Tri-stated
Disabled
NOTE:
1. This mode requires external logic to disable the U-Bus transceiver for access to 3F7h/377h. This is necessary due to
potential contention between the Utility Bus buffer and a floppy on the ISA Bus driving the system bus at the same time
during shared I/O accesses.
Coprocessor Error Support
If bit 5 in the ISA Clock Divisor Register is set to a one, the SIO/SIO.A will support coprocessor error reporting
through the FERR#/IRQ13 signal. FERR# is tied directly to the coprocessor error signal of the CPU. If FERR# is
driven active in this mode (coprocessor error detected by the CPU), an internal IRQ13 is generated and the INT
output from the SIO/SIO.A is driven active. When a write to I/O location F0h is detected, the SIO/SIO.A negates
IRQ13 and drives IGNNE# active. IGNNE# remains active until FERR# is driven inactive. Note that IGNNE# is
not generated unless FERR# is active.
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