82378ZB Datasheet, PDF (13/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
2.1. PCI Bus Interface Signals
Signal Name Type
Description
PCICLK
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PCI CLOCK: PCICLK provides timing for all transactions on the PCI Bus. All other
PCI signals are sampled on the rising edge of PCICLK, and all timing parameters
are defined with respect to this edge. Frequencies supported by the SIO/SIO.A
include 25 and 33 MHz.
PCIRST#
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PCI RESET: PCIRST# forces the SIO/SIO.A to a known state. AD[31:0],
C/BE[3:0]#, and PAR are always driven low by the SIO/SIO.A synchronously from
the leading edge of PCIRST#. The SIO/SIO.A always tri-states these signals from
the trailing edge of PCIRST#. If the internal arbiter is enabled (CPUREQ# sampled
high on the trailing edge of PCIRST#), the SIO/SIO.A will drive these signals low
again (synchronously 2-5 PCICLKs later) until the bus is given to another master. If
the internal arbiter is disabled (CPUREQ# sampled low on the trailing edge of
PCIRST#), these signals remain tri-stated until the SIO/SIO.A is required to drive
them valid as a master or slave.
FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, MEMREQ#, FLSHREQ#,
CPUGNT#, GNT0#/SIOREQ#, and GNT1#/RESUME# are tri-stated from the
leading edge of PCIRST#. FRAME#, IRDY#, TRDY#, STOP#, and DEVSEL#
remain tri-stated until driven by the SIO/SIO.A as either a master or a slave.
MEMREQ#, FLSHREQ#, CPUGNT#, GNT0#/SIOREQ#, and GNT1#/RESUME#
are tri-stated until driven by the SIO/SIO.A. After PCIRST#, MEMREQ# and
FLSHREQ# are driven inactive asynchronously from PCIRST# inactive. CPUGNT#,
GNT0#/SIOREQ#, and GNT1#/RESUME# are driven based on the arbitration
scheme and the asserted REQx#'s.
All registers are set to their default values. PCIRST# may be asynchronous to
PCICLK when asserted or negated. Although asynchronous, negation must be a
clean, bounce-free edge. Note that PCIRST# must be asserted for more than 1 µs.
AD[31:0]
I/O
PCI ADDRESS/DATA. The standard PCI address and data lines. The address is
driven with FRAME# assertion and data is driven or received in following clocks.
C/BE[3:0]# I/O
BUS COMMAND AND BYTE ENABLES: The command is driven with FRAME#
assertion. Byte enables corresponding to supplied or requested data are driven on
following clocks.
FRAME#
I/O
(s/t/s)
CYCLE FRAME: Assertion indicates the address phase of a PCI transfer. Negation
indicates that one more data transfer is desired by the cycle initiator. FRAME# is tri-
stated from the leading edge of PCIRST#.
TRDY#
I/O
TARGET READY: Asserted when the target is ready for a data transfer. TRDY# is
(s/t/s) tri-stated from the leading edge of PCIRST#.
IRDY#
I/O
INITIATOR READY: Asserted when the initiator is ready for a data transfer. IRDY#
(s/t/s) is tri-stated from the leading edge of PCIRST#.
STOP#
I/O
STOP: Asserted by the target to request the master to stop the current transaction.
(s/t/s) STOP# is tri-stated from the leading edge of PCIRST#.
LOCK#
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LOCK: LOCK# indicates an atomic operation that may require multiple transactions
to complete. LOCK# is always an input to the SIO/SIO.A.
IDSEL
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INITIALIZATION DEVICE SELECT: IDSEL is used as a chip select during
configuration read and write transactions.
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