82378ZB Datasheet, PDF (83/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
3.7.4. APICID—I/O APIC VERSION REGISTER (82379AB Only)
Address Offset:
Default Value:
Attribute:
01h
000F0011h
Read Only
The I/O APIC Version Register identifies the APIC hardware version. Software can use this to provide
compatibility between different APIC implementations and their versions. In addition, this register provides the
maximum number of entries in the I/O Redirection Table.
Bit
31:24
23:16
15:8
7:0
Description
Reserved
Maximum Redirection Entry: This field contains the entry number (0 being the lowest entry) of the
highest entry in the I/O Redirection Table. The value is equal to the number of interrupt input pins
minus one of this I/O APIC. The range of values is 0 through 239. For the 82379AB, this value is 0Fh.
Reserved
APIC VERSION: This 8 bit field identifies the implementation version. The version number for the
82379AB is 11h.
3.7.5. APICARB—I/O APIC ARBITRATION REGISTER (82379AB Only)
Address Offset:
Default Value:
Attribute:
02h
00000000h
Read Only
The APICARB Register contains the bus arbitration priority for the I/O APIC. This register is loaded when the I/O
APIC ID Register is written.
Bit
Description
31:28 Reserved
27:24 I/O APIC Arbitration Identification: This 4 bit field contains the I/O APIC arbitration priority
identification.
23:0 Reserved
3.7.6. IOREDTBL[15:0]—I/O REDIRECTION TABLE REGISTERS (82379AB Only)
Address Offset:
Default Value:
Attribute:
10-11h (IOREDTBL0)
12-13h (IOREDTBL1)
14-15h (IOREDTBL2)
16-17h (IOREDTBL3)
18-19h (IOREDTBL4)
1A-1Bh (IOREDTBL5)
xx000000 00010xxxh
Read/Write
1C-1Dh (IOREDTBL6) 26-27h (IOREDTBL11)
1E-1Fh (IOREDTBL7) 28-29h (IOREDTBL12)
20-21h (IOREDTBL8) 2A-2Bh (IOREDTBL13)
22-23h (IOREDTBL9) 2C-2Dh (IOREDTBL14)
24-25h (IOREDTBL10) 2E-2Fh (IOREDTBL15)
Each of the 16 I/O Redirection Table entry registers is a dedicated entry for each interrupt input pin. Unlike IRQ
pins of the 8259A, the notion of interrupt priority is completely unrelated to the position of the physical interrupt
input pin on the APIC. Instead, software determines the vector (and therefore the priority) for each corresponding
interrupt input pin. For each interrupt pin, the operating system can also specify the signal polarity (low active or
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